Dini Group DN9002K10PCI, User Manual

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H A R D W A R E
DN9002K10PCI User Guide www.dinigroup.com 134
Special purpose pins are d
below. escribed
CB
an
is
associated with the header.
The GCC signal driven from each FPGA connects to a global clock buffer and can be used by
all of the FPGAs on the DN9002K10PCI. (EXT0 and EXT1 networks). Since daughter cards
25.2.2 CC, VREF, DCI
Some of the signals connected to
the daughter card expansion
headers are “clock-capable”; the
inputs on the Virtex 5 FPGA can
be used for source-synchronous
clocking. In the schematic and
customer netlist on the user CD,
these pins contain a “_C” in the
pin name.
Pins declared in the above
diagram that are underlined are
connected to “VREF” pins on
the Virtex 5 FPGA. These FPGA
pins are used to supply a voltage
reference used as the threshold
voltage for the signals on that
bank. The use of these pins is
only necessary when using
threshold standards, such as
SSTL.
DCI is used on all FPGA IO
banks connected to a daughter
card header. The reference
resistance is 50 Ohms. Each
Virtex 5 bank that is connected to
a header DCI in enabled.
25.2.3 Global clocks
The daughter card pin out defines
6 clock output pins. These clock
outputs are intended to be used a
3 differential signals (LVDS).
Two clock signals GCA and G
connect to the “GC” clock inputs
on the FPGA. These clocks c
be used only by the FPGA that