Dini Group DN9002K10PCI, User Manual

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H A R D W A R E
22.1 5.0V
The 5.0V rail is used to generate most other voltages on the board. The only places where 5.0V
is used directly are the daughtercards, and the cooling fan power connectors.
Below is a list of the maximum power draw of each of the 5.0V loads on the DN9002K10PCI.
Rail Max Current Uses 5V current
1.0V_A 25 Internal FPGA power 5
1.0V_B 25 Internal FPGA power 5
1.8V 2 DIMM B 1
2.5V 9 Spartan 3 (1.2V) 4.5
FPGA IO
FPGA Aux power
Daughtercards 10 10
TOTAL 25.5
The total possible power requirement of the DN9002K10PCI is 25.5A on 5.0V (127W). This
rate of power dissipation is well beyond the cooling capabilities of the heat dissipation provided.
Therefore, the user must limit the power dissipated by his design. More typically, each FPGA
would only use 10A, and daughtercards would use little or no power on 5.0V. Under these
conditions, the 5.0V power requirement is only 4A (20W).
22.2 3.3V
3.3V is used by the DN9002K10PCI to supply the clock distribution network, the configuration
logic (Micro controller and Spartan 3 FPGA), and daughtercard power.
The maximum power requirement for the DN9002K10PCI on 3.3V is 1A. 3.3V is taken
directly from the ATX power supply or from the PCI slot.
22.3 2.5V
2.5V power is generated from the 5.0V using a 30A power supply.
22.4 Ground
All ground (0V) voltages on the DN9002K10PCI are shared. A monolithic ground design
strategy was used. The nets GND_SHIELD and GND_ANALOG are directly connected to
the ground plane.
DN9002K10PCI User Guide www.dinigroup.com 119