dimtel
dimtel
4.2
Selftest
46 FID c l o c k d e l a y t e m p e r a t u r e r i s e ( deg C ) :
5 . 8
47 DAC c l o c k d e l a y t e m p e r a t u r e r i s e ( deg C ) :
6 . 1
Line 1
The utility terminates the IOC process to gain access to the FPGA
interface.
Lines 3–8
Contents of the FPGA config register are parsed and printed out.
Line 12
Test of the data acquisition blockRAM.
Line 13
External SRAM test.
Line 14
General-purpose digital I/O is tested.
Line 15
Presence of the RF clock is verified as well as the lock status of the
Lines 17–25
A test of the low-speed DAC and ADC system. This test
uses 7 channels of the DAC to drive different voltages and measures
the voltages using the ADC. The test measures several parameters for
each channel. Test code finds the minimum DAC setting that does not
saturate the ADC. ADC reading (column 2) and the dead-reckoned
DAC output (column 3) are printed out in millivolts. Next the DAC is
set to 0 and the ADC reading (offset, column 4) is taken. Finally, the
code finds the maximum DAC setting that does not saturate the ADC.
Lines 27–31
This portion of the test uses channel 7 of the slow DAC to
adjust the output offset of the high-speed DAC ˙
The code extracts the
reading from the high-speed ADC at the positive and negative extremes
of the offset DAC. Next the code finds the offset DAC setting that
minimizes the high-speed ADC measurement. This setting should be
very close to the factory determined value used in EPICS to null the
high-speed DAC output.
Lines 33–37
This fragment verifies the response via the high-speed DAC.
To do so it finds the DAC settings to obtain readings of
±
120 and 0
counts from the ADC.
Lines 39–47
Environmental monitor readings are taken and displayed.
The output of
selftest
utility can be redirected to a file and compared
to the factory measurement provided in
/root/factory.selftest
.
After testing restart the IOC process by typing:
[root@IOC ~]# iGp_start
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