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3
BIOS Setup
PCI1 Master 0 WS Write and PCI2 Master 0 WS Write
When enabled, writes to the PCI bus are executed with zero wait
state.
PCI1 Post Write and PCI2 Post Write
The options are Enabled and Disabled.
VLink 8x Support
Enabled
The speed of VLink which links the North Bridge
and South Bridge is 8x.
Disabled
The speed of VLink which links the North Bridge
and South Bridge is 4x.
PCI Delay Transaction
When enabled, this function frees up the PCI bus for other PCI
masters during the PCI-to-ISA transactions. This allows PCI and ISA
buses to be used more efficiently and prevents degradation of
performance on the PCI bus when ISA accesses are made.
3.1.3.4 System BIOS Cacheable
When this field is enabled, accesses to the system BIOS ROM ad-
dressed at F0000H-FFFFFH are cached, provided that the cache
controller is enabled. The larger the range of the Cache RAM, the
higher the efficiency of the system.
3.1.3.5 Video RAM Cacheable
When enabled, it allows the video RAM to be cacheable thus pro-
viding better video performance. If your graphics card does not sup-
por t this function, leave this field in its default setting - Disabled.