PUMA Station Board
Burst Cycles
The 486 microprocessor accepts burst cycles for any bus
request that requires more than one data cycle. During
burst cycles, a new data item is strobed into the 486
microprocessor for every clock rather than every other
clock as in non-burst cycles.
TACT84543 EISA Bus Control Unit
The EB3486-TN system board uses the 82358 EISA
Bus Controller that supports the following:
• Provides EISA/ISA bus cycle compatibility
• Interfaces host (CPU) bus to EISA/ISA bus
• Translates host bus cycles to EISA/ISA bus cycles
• Generates ISA signals for EISA masters
• Generates EISA signals for ISA masters
• Supports 8-, 16-, or 32-bit DMA cycles
• Supports host and EISA/ISA refresh cycles
• Generates control signals for address and data buffers
• Supports byte assembly/disassembly for 8-, 16-, or 32-
bit data transfers
• Supports I/O recovery mechanism
E-5
u
Appendix E