Denon PMA-50, Service Manual

Page: 63 / 93

SEMICONDUCTORS
Only major semiconductors are shown, general semiconductors etc. are omitted to list.
The semiconductor which described a detailed drawing in a schematic diagram are omitted to list.
1. IC's
STM32F103ZG(IC214)
Block diagram
Pinouts and pin descriptions STM32F103xF, STM32F103xG
26/120 Doc ID 16554 Rev 3
Figure 4. STM32F103xF and STM32F103xG XL-density performance line LQFP144 pinout
V
DD_3
V
SS_
3
PE1 PE0 PB9 PB8 B
OOT0
PB7 PB6 PB5 PB4 PB3 P
G
15
V
DD_11
V
S
S
_11
P
G
14
P
G
13
P
G
12
P
G
11
P
G
10
P
G9
P
D7
P
D6
V
DD_10
V
S
S
_10
P
D5
P
D4
P
D3
P
D2
P
D1
P
D0
P
C1
2
P
C1
1
P
C1
0
PA1
5
PA1
4
PE2
V
DD_2
PE3
V
SS_2
PE4
NC
PE5
PA13
PE6
PA12
VBAT
PA11
PC13-TAMPER-RTC
PA10
PC14-OSC32_IN
PA9
PC15-OSC32_OUT
PA8
PF0
PC9
PF1
PC8
PF2
PC7
PF3
PC6
PF4
V
DD_9
PF5
V
SS_9
V
SS_5
PG8
V
DD_5
PG7
PF6
PG6
PF7
PG5
PF8
PG4
PF9
PG3
PF10
PG2
OSC_IN
PD15
OSC_OUT
PD14
NRST
V
DD_8
PC0
V
SS_8
PC1
PD13
PC2
PD12
PC3
PD11
V
SSA
PD10
V
REF-
PD9
V
REF+
PD8
V
DDA
PB15
PA0-WKUP
PB14
PA1
PB13
PA2
PB12
PA3
V
SS_
4
V
DD_4
PA4 PA5 PA6 PA7 P
C4
P
C5
PB0 PB1 PB2
PF1
1
PF1
2
VSS_
6
V
DD_6
PF1
3
PF1
4
PF1
5
P
G0
P
G1
PE7 PE8 PE9
V
SS_
7
V
DD_7
PE1
0
PE1
1
PE1
2
PE1
3
PE1
4
PE1
5
PB1
0
PB1
1
V
SS_
1
V
DD_1
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 109
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25 108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 72
LQFP144
120 119 118 117 116 115 114 113 112 111 110
61 62 63 64 65 66 67 68 69 70 71
26
27
28
29
30
31
32
33
34
35
36
83
82
81
80
79
78
77
76
75
74
73
ai14667
Description STM32F103xF, STM32F103xG
12/120 Doc ID 16554 Rev 3
Figure 1. STM32F103xF and STM32F103xG performance line block diagram
1. T
A
= –40 °C to +85 °C (suffix 6, see Table 73 ) or –40 °C to +105 °C (suffix 7, see Table 73 ), junction temperature up to
105 °C or 125 °C, respectively.
2. AF = alternate function on I/O port pin.
PA[15:0]
EXT.IT
WWDG
NVIC
12 b it ADC1
8 ADIN s common
JTDI
JTCK/ S WCLK
JTM S / S WDAT
NJTR S T
JTDO
=2 t o 3 .6V
112 AF
AHB2
MO S I/ S D,MI S O,
WKUP
Fm
a x: 4
8 /72 MHz
V
SS
S CL, S DA, S MBA
I2C2
GP DMA1
XTAL O S C
4-16 MHz
XTAL 3 2 kHz
A
P
B
1:
F
m
a
x=2
4
/
3
6
MH
z
HCLK
PCLK1
as AF
Fl as h1 512 KB
VOLT. REG.
3 . 3 V TO 1. 8 V
POWER
B a ck u p interf a ce
as AF
B
u
s
m
a
trix
64 b it
RTC
RC H S
Cortex-M 3 CPU
I b u s
D bus
o
b
l
S RAM 512B
U S ART1
U S ART2
S PI2/I2 S 2
b xCAN device
7 ch a nnel s
B a ck u p
reg
4 ch a nnel s
TIM1
4 compl.
S CL, S DA, S MBA
I2C1
as AF
RX,TX, CT S , RT S ,
U S ART 3
Temp s en s or
4 Ch, ETR as AF
FCLK
RC L S
S t a nd b y
IWDG
@V S W
POR / PDR
S UPPLY
@VDDA
VBAT=1. 8 V to 3 .6V
CK as AF
RX,TX, CT S , RT S ,
CK as AF
RX,TX, CT S , RT S ,
CK as AF
A
PB
2:
F
m
a
x=4
8
/72
MH
z
NVIC
S PI1
MO S I,MI S O,
S CK,N SS as AF
12 b it ADC2
IF
IF
interf a ce
S UPERVI S ION
PVD
Re s et
Int
AWU
POR
TAMPER-RTC
S y s tem
S CK/CK,N SS /W S ,
UART4
RX,TX as AF
UART5
RX,TX as AF
Re s et &
clock
controller
PCLK2
PLL
12 b it DAC1 IF IF
IF
12 b it DAC2
DAC1_OUT as AF
DAC2_OUT as AF
to the 3 ADC s
8 ADIN s common
to the ADC1 & 2
GP DMA2
5 ch
a nnel s
(ALARM OUT)
MCLK as AF
MO S I/ S D,MI S O,
S CK/CK,N SS /W S ,
MCLK as AF
S WJTAG
TPIU
ETM
Tr a ce/Trig
TRACECLK
TRACED[0: 3 ]
as AF
U S BDM/CAN_RX
U S BDP/CAN_TX
S DIO
F S MC
PCLK 3
S RAM
96 K b yte
64 b it
12 b it ADC 3 IF
5 ADIN s on ADC 3
4
4 compl.
BKIN, ETR inp u t as AF
PB[15:0]
PC[15:0]
PD[15:0]
PE[15:0]
PF[15:0]
PG[15:0]
MPU
2 as AF
1 as AF
1 as AF
4 Ch, ETR as AF
4 Ch, ETR as AF
4 Ch, ETR as AF
D[7:0], CMD
CK as AF
Fl as h2 512 KB
A[25:0]
D[15:0]
CLK
NOE
NWE
NE[ 3 :0]
NBL[1:0]
NWAIT
NL
as AF
ch a nnel s
ch a nnel s
ch a nnel s
ch a nnel s
ch a nnel
ch a nnel
TIM 8
TIM9
TIM10
TIM11
V
REF+
V
REF–
TIM6
TIM7
TIM2
TIM 3
TIM4
TIM5
TIM12
TIM1 3
TIM14
O S C_IN
O S C_OUT
O S C 3 2_IN
O S C 3 2_OUT
VDD
@VDD
NR S T
VDDA
V
SS A
VDD
@VDD
@VDDA
@VDDA
Fl
as
h
interf
a
ce
Fl
as
h
interf
a
ce
o
b
l
2 ch a nnel s as AF
1 ch a nnel as AF
1 ch a nnel as AF
a i17 3 52
@VDDA
GPIO port A
GPIO port B
GPIO port C
GPIO port D
GPIO port E
GPIO port F
GPIO port G
APB 3 APB2 APB1
BKIN, ETR inp u t as AF
U S B 2.0 F S device
S PI 3 /I2 S3
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