Denon AVR-2313, Service Manual

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A3V56S30FTP-G6 Block Diagram
LAN8720A (HDMI:U2802)
A3V56S30FTP
A3V56S40FTP
256M Single Data Rate Synchronous DRAM
Revision 1.1 Mar., 2010
Page 3 / 39
Note:This figure shows the A3V56S30FTP
The A3V56S40FTP configuration is 8192x512x16 of cell array and DQ0-15
Type Designation Code
A 3Ｖ
56
Ｓ４０F ＴＰ－
G6
Speed Grade 75
：
133MHz@CL=3
7
：
143MHz@CL=3
6
：
166MHz@CL=3
G
：
Green
Package Type TP
：
TSOP (II)
Process Generation
Function Reserved for Future Use
Organization 2
n
3
：
x8, 4
：
x16
SDR Synchronous DRAM
Density 56
：
256M bits
Interface V
：
LVTTL
Memory Style (DRAM)
Zentel DRAM
Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support
Datasheet
SMSC LAN8720A/LAN8720Ai 9 Revision 1.3 (04-20-11)
DATASHEET
Chapter 2 Pin Description and Configuration
Note: When a lower case “n” is used at the beginning of the signal name, it indicates that the signal
is active low. For example, nRST indica tes that the reset signal is active low.
Note: The buffer type for each signal is indicated in the BUFFER TYPE column. A description of the
buffer types is provided in Section 2.2 .
Figure 2.1 24-QFN Pin Assignments (TOP VIEW)
VSS
NOTE: Exposed pad (VSS) on bottom of package must be connected to ground
SMSC
LAN8720A/LAN8720Ai
24 PIN QFN
(TOP VIEW)
MDIO
1 2 3 4 5 6
7
8
9
10
11
12
18 17 16 15 14 13
24
23
22
21
20
19
VDD
CR
XTAL1/
CL
KI
N
XT
AL2
LED1/
REGOFF
LED2/
nINTSEL
VDD2A
TXD1 TXD0 TXEN nRST nI
NT
/RE
FCLKO
MDC
VDD1A
TXN
TXP
RXN
RXP
RBIAS
CRS_DV/MODE2
RXER/PHYAD0
VDDIO
RXD0/MODE0
RXD1/MODE1