16
AVC-A1D/AVR-5700
TMP93CS41F
(DS: IC301)
Name
Function
TMP93CS41F Terminal Function
Pin
No.
1
V REFL
A/D ref. GND
2
A Vss
←
A/D GND
3
A Vcc
←
AD +5V
4
_NMI
I
Not used (fixed to H)
5
P70/TI0
_DEMOD RESET
O
C
Ed
L
L
Demodulator reset output (L: Reset)
6
P71/TO1
DEMOD ON
O
C
Ed
L
L
Demodulator osc. control output (H: Osc.)
7
P72/TO2
FAN1
O
C
Ed
L
L
FAN control output (H: ON, L: OFF)
8
P73/TO3
FAN2
O
C
Ed
L
L
FAN control output (H: Hi, L: Low & off)
9
P80/INT4/TI4
B.DOWN_
I
Eu
E
↓
&L
Z
Power down detect (L: Detected)
10
P81/INT5/TI5
DSP ACK
I
E
↑
&L
Host I/F comm. response input (L: OK)
11
P82/TO4
AC-3 RF DET
I
E
↓
&L
AC-3 RF signal judge input (L: AC-3 data input)
12
P83/TO5
_REQ
O
C
Eu
H
L
MAIN-SUB CPU comm. control output (L: Comm. request from
sub)
13
P84/INT6/TI6
_ACK
I
Eu
E
↓
&L
MAIN-SUB CPU comm. control input (L: Ack. return from main)
14
P85/INT7/TI7
ERR
I
E
↑
&L
DIR control input terminal (LC89055Q)( H: ERR)
15
P86/TO6
_DSP RESET
O
C
Ed
L
L
DSP reset output terminal (L: Reset)
16
P97/INT0
_CS
I
Ed
E
↑
&L
DIR control input terminal (LC89055Q), when CH status change L
•¨
H
17
P90/TXD0
SI
O
C
MAIN-SUB CPU comm. control terminal (data output)
18
P91/RXD0
SO
I
MAIN-SUB CPU comm. control terminal (data input)
C
MAIN-SUB CPU comm. control terminal (I2C clock in/output)
C
Z
L
(DXP6001) control data output
Lv
DIR control input terminal (LC89055Q) control data input
C
Z
L
DIR control terminal (LC89055Q) control clock output
Fixed to +5V
C
Eu
+5V
GND
X
′
tal connection
X
′
tal connection
Fixed to +5V
Eu
Lv
L
Reset input (controlled by main CPU)
31
P96/XT1
A/D RESET
O
N
Eu
H
H
A/D control terminal (L: Reset)
32
P97/XT2
DAC RESET
O
N
Eu
H
H
D/A control terminal (L: Reset)
33
TEST1
←
Ι
Connected to TEST2
34
TEST2
←
Ι
Connected to TEST1
35
PA0
DINA
O
C
Ed
L
L
Digital input switching control output
36
PA1
DINB
O
C
Ed
L
L
Digital input switching control output
37
PA2
DINC
O
C
Ed
L
L
Digital input switching control output
38
PA3
DIND
O
C
Ed
L
L
Digital input switching control output
39
PA4
DINE
O
C
Ed
L
L
Digital input switching control output
40
PA5
DOUTA
O
C
Ed
L
L
Digital input switching control output
Symbol
I/O
Type
Op
Det
Res
Init
75
76
100
1
25
26
50
51
Name
Function
Pin
No.
41
PA6
DOUTB
O
C
Ed
L
L
Digital input switching control output
42
PA7/SCOUT
DOUTC
O
C
Ed
L
L
Digital input switching control output
43
ALE
←
O
C
L
L
Address latch enable
44
Vcc
+5V
45
P00/AD0
AD0
I/O
C
Z
L
EPROM data in D0 / address out A0
46
P01/AD1
AD1
I/O
C
Z
L
EPROM data in D1 / address out A1
47
P02/AD2
AD2
I/O
C
Z
L
EPROM data in D2 / address out A2
48
P03/AD3
AD3
I/O
C
Z
L
EPROM data in D3 / address out A3
49
P04/AD4
AD4
I/O
C
Z
L
EPROM data in D4 / address out A4
50
P05/AD5
AD5
I/O
C
Z
L
EPROM data in D5 / address out A5
51
P06/AD6
AD6
I/O
C
Z
L
EPROM data in D6 / address out A6
52
P07/AD7
AD7
I/O
C
Z
L
EPROM data in D7 / address out A7
53
P10/AD8/A8
A8
O
C
Z
L
EPROM address out A8
54
P11/AD9/A9
A9
O
C
Z
L
EPROM address out A9
55
P12/AD10/A10
A10
O
C
Z
L
EPROM address out A10
56
P13/AD11/A11
A11
O
C
Z
L
EPROM address out A11
57
P14/AD12/A12
A12
O
C
Z
L
EPROM address out A12
58
P15/AD13/A13
A13
O
C
Z
L
EPROM address out A13
59
P16/AD14/A14
A14
O
C
Z
L
EPROM address out A14
60
P17/AD15/A15
A15
O
C
Z
L
EPROM address out A15
61
_WDTOUT
←
O
C
Z
H
Watch dog output
62
Vss
←
GND
63
Vcc
←
+5V
64
P20/A0/A16
A16
O
C
Z
L
EPROM address out A16
65
P21/A1/A17
DF CLK
O
C
Z
L
(DXP6001) control clock output
66
P22/A2/A18
ADIRCE
O
C
Z
L
DIR control terminal (LC89055Q) control chip enable output
67
P23/A3/A19
DIR MOSI
O
C
Z
L
DIR control terminal (LC89055Q) control data output
68
P24/A4/A20
DF STB1
O
C
Z
L
(DXP6001) control strobe output
69
P25/A5/A21
FGAIN
O
C
Ed
L
L
IV AMP gain switching control output (L: Sub-woofer on)
70
P26/A6/A22
HDCD
O
C
Ed
L
L
HDCD control terminal (fixed to L)
71
P27/A7/A23
SEL CK
O
C
Ed
Z
L
ADC/DIR data clock switching control terminal (L: ADC)
72
P30/_RD
_RD
O
C
Ed
Z
L
Flash memory control terminal
73
P31/_WR
_WR
O
C
Ed
Z
L
Flash memory control terminal
74
P32/_HWR
CSI
I
Ed
Lv
DIR control input terminal (DIR1700) (L: PCM)
75
P33/_WAIT
ERR MUTE_
O
C
Ed
L
L
Pop noise preventive mute control output (L: Mute)
76
P34/_BUSRQ
_DSP REQUEST
O
C
Ed
Z
L
(ADSP21061L-A:IRQ1_) host I/F interrupt request output (L: REQ)
77
P35/_BUSRQ
DIG.(AC39 MUTE
O
C
Ed
Z
L
Digital mute control output (L: AC-3 or DTS decode enable)
78
P36/_R/W
WRITE
O
C
Z
L
DSP comm. control terminal (H: Data write)
79
P37/_RAS
DIR RESET
O
C
Z
L
DIR control output (LC89055Q) (L: Reset)
80
P40/\CS0/_CAS0 FLAG 1B
I
Lv
(ADSP21061L-B:FLAG1B) input
81
P41/_CS1/_CAS1
LFE PRESENCE
I
Lv
(ADSP21061L-B:FLAG0B) LFE signal detect input, H: LFE
detected
82
P42/_CS2/_CAS2
_CS0
O
C
Z
L
Flash memory control terminal
83
P60/PG00
I/01
I/O
C
Z
L
DSP comm. terminal (ADSP21061L: D16)
84
P61/PG01
I/02
I/O
C
Z
L
DSP comm. terminal (ADSP21061L: D17)
85
P62/PG02
I/03
I/O
C
Z
L
DSP comm. terminal (ADSP21061L: D18)
86
P63/PG03
I/04
I/O
C
Z
L
DSP comm. terminal (ADSP21061L: D19)
87
P64/PG10
I/05
I/O
C
Z
L
DSP comm. terminal (ADSP21061L: D20)
88
P65/PG11
I/06
I/O
C
Z
L
DSP comm. terminal (ADSP21061L: D21)
89
P66/PG12
I/07
I/O
C
Z
L
DSP comm. terminal (ADSP21061L: D22)
90
P67/PG13
I/08
I/O
C
Z
L
DSP comm. terminal (ADSP21061L: D23)
91
Vss
←
GND
92
P50/AN0
AUDIO LEVEL
I
Eu
Lv
Z
Signal level detect, set to A/D input
93
P51/AN1
POSI (FAN)
I
Eu
Lv
Z
Temperature detect, set to A/D input
94
P52/AN2
EMP
I
Lv
H: EMP on
95
P53/AN3
96K DET
I
Lv
96k signal detect input, H: 96k
96
P54/AN4
BUSY1
I
Lv
(ADSP21061L-A:FLAG2A)
97
P55/AN5
FLAG 3A
I
Lv
(ADSP21061L-A:FLAG3A)
98
P56/AN6
BUSY2
I
Lv
(ADSP21061L-B:FLAG2B) input
99
P57/AN7
I
Lv
100
V REFH
←
AD ref. +5V
Symbol
I/O
Type
Op
Det
Res
Init
w w w . x i a o y u 1 6 3 . c o m
Q Q 3 7 6 3 1 5 1 5 0
9
9
2
8
9
4
2
9
8
T E L
1 3 9 4 2 2 9 6 5 1 3
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299
Summary of Contents for AVC-A1D
Page 87: ......
