P112 Single Board Computer
Assembly and Operation Manual
Revision 1.1
David Griffith
Wednesday May 10, 2006
1
Page 1: ...P112 Single Board Computer Assembly and Operation Manual Revision 1 1 David Griffith Wednesday May 10 2006 1 ...
Page 2: ...This page is intentionally left blank 2 ...
Page 3: ...dering the First Parts 12 3 4 Soldering Everything Else 12 4 Setting Up 14 4 1 Jumper Settings 14 4 2 Terminal Settings 15 4 3 Disk Drives 15 4 4 Powering Up 16 5 Debugger 18 5 1 Help Function 18 5 2 Set Breakpoint 19 5 3 Display Set Memory 19 5 4 Go Run Program 20 5 5 Trace instructions 20 5 6 Display Set Registers 21 5 7 Loading Files 21 5 8 Input from Port 22 5 9 Output to Port 22 5 10 System B...
Page 4: ...tte Port 33 7 9 Printer Port 33 8 Major Components 34 8 1 CPU Chip 34 8 2 I O Combination 34 8 2 1 Port Addressing 34 8 3 Flash ROM 35 8 4 Realtime Clock 35 9 Connector Pins 36 9 1 P1 RAM Size Selector 36 9 2 P2 DMA Requests 36 9 3 P3 Flash Bootload Selector 36 9 4 P4 Serial Port 1 38 9 5 P5 SYNC Jumper 38 9 6 P6 Power Supply Reset 39 9 7 P7 Parallel Printer 39 9 8 P8 Serial Port 2 40 9 9 P9 Disk ...
Page 5: ...10 Software 47 10 1 Z System and ZSDOS 47 10 2 Flash Programmer 48 10 3 DISKCOPY 48 11 Warranty Etc 49 5 ...
Page 6: ...ced by David Griffith After a lot of work unexpected problems and gnashing of teeth kits started to ship in late 2005 Most of the content of this manual is taken directly and usually verbatim from two PDF files produced by David Brooks in 1996 as documentation for the first run of P112 boards Other content comes from documentation from related utilities written specifically for the P112 This intro...
Page 7: ...hings that can be found at a typical consumer elec tronics parts shop Other things you might want to complete this project can be easily found on auction websites like Ebay You might also have much of these things already Soldering equipment All of these soldering items can be found at Radio Shack http www radioshack com A soldering iron drawing 15 to 30 watts is plenty powerful for this job Don t...
Page 8: ...inal emulator program Floppy drives You ll need at least one floppy drive Two is nicer You can have as many as four but two drives is best This board can use any internal 34 pin interface floppy drive that an x86 PC can Purists might want to use 5 25 drives 5 25 disks can be a bit hard to find but it shouldn t be a big problem Since this kit includes only 3 5 disks use 3 5 drives unless you know w...
Page 9: ...S 232 terminals may be connected to P4 and P8 with the primary terminal being at P4 A 10 conductor ribbon cable connects via a standard IDC socket to the board The tenth conductor is clipped off and the rest are crimped or soldered to a standard IDC DB 9 plug as follows 9 8 7 6 5 4 3 2 1 1 2 3 4 5 6 7 8 9 Serial connector wired straight through solder side view This generates the same pinout as a ...
Page 10: ...nnection from P9 or P10 to the first drive then cores 10 16 reversed in the path to the 2nd drive In P9 the first drive will be Drive 0 and the second Drive 1 From P10 they are Drives 3 and 2 similarly note the reversed assignment In other words a standard floppy ribbon cable is what you need This cable is not included Sorry I couldn t find enough in large quantities 2 1 4 Parallel Port Cable A st...
Page 11: ... Qty Markings Location 4 7k Ω 3 yellow violet red R3 R4 R11 10k Ω 3 brown black orange R5 R7 R10 27k Ω 1 red violet orange R9 47k Ω 6 yellow violet orange R1 R2 R6 R8 R12 R13 Semiconductors Qty Location 74hct00 1 U5 74act02 1 U8 74act139 1 U11 DS1302 RTC chip 1 U6 TL7705ACP TI reset gen 1 U15 LT1133 RS232 tx rx 2 U7 U10 62256 Static RAM 32kb 2 U2 U3 29c256 Flash ROM 32kb 1 U4 Crystals Qty Location...
Page 12: ...be held together with a jumper block while soldering Sockets Qty Location DIN48 expansion white 1 J1 8 pin DIP 2 U6 U15 14 pin DIP 2 U5 U8 16 pin DIP 1 U11 24 pin DIP 2 U7 U10 32 pin DIP 3 U2 U3 U4 20mm button cell holder 1 B1 Misc Parts Qty Location Jumper block 10 2032 lithium coin cell 1 B1 Chassis mount serial cable 2 P4 P8 Not included Qty Location NMF0512S 5 12V converter 1 U12 The 5 12V con...
Page 13: ...ue and the value is written on the piece of tape holding its leads together There are a lot of bypass capacitors all wrapped up in a bouquet The 22ρ units are taped together side by side with clear tape and resemble match heads Tantalum capacitors are a bit more difficult The 22µ units are usually larger and often have their leads bent out to more easily fit in their holes The 1µ units look a bit ...
Page 14: ...re proceeding Chip Sockets The sockets for U2 U3 and U4 appear to be of the press fit variety This isn t a problem as long as you don t want to remove it after putting it in its holes Firmly but gently press them into place and solder as usual For the other sockets tape them down with some masking tape before flipping the board over to solder them If you re brave you can use a finger and tack sold...
Page 15: ...brave you can hold them in with a finger and tack down the ends One header P1 is made up of a single row of three pins and a single pin While soldering put a jumper block on this to hold it together Tall Crystals There s nothing special about these Just make sure you put each crystal where it needs to go Battery Holder A holder for a 2032 lithium coin cell was substituted for the 1 2AA cell origi ...
Page 16: ...kit comes with 28 pin parts The sockets are 32 pin to allow one to install larger SRAMs and ROMs Make sure you install these chips with their bottom ends flush with the bottom ends of the sockets If mounted with their tops flush you probably won t let out the Magic Smoke but it definitely will not work correctly if at all Install the rest of the chips and insert the lithium battery into its holder...
Page 17: ...rminal console to CP M connects to P4 Use a null modem cable the nulled pigtail described in section 2 1 2 or short pins 1 6 and 7 of P4 together This is necessary to force the modem control lines active without which the serial port will not operate 4 3 Disk Drives The board can run a variety of PC AT type 3 5 drives out of the box Specifically the drives should be jumpered with DS1 active as is ...
Page 18: ... accessible The lower 32kB is overlaid by the ROM With a 3 5 drive connected as Drive 0 and the supplied disk loaded you can type Z return at any Debug prompt to boot the system The first time you boot the ZSDOS system boot disk you should see the following OS Loaded Booting D X Designs P112 Bios V3 ZCPR3 LDR Version 1 6 Loading Z33 ENV ZEX Version 3 1 A0 ZEX ldr z33 z3t z33 ndr z33 rcp z33 fcp ZC...
Page 19: ...he file You can also delete this file NOTE TXT A0 BASE ZEX fi A0 BASE ZEX Done A0 BASE At this point you should follow the directions given above so the system knows what terminal you are using Z3CAP is a library analogous to the Termcap library on Unix systems These libraries provide an abstraction layer to allow programs to support a wide variety of terminals on the fly Because standard CP M doe...
Page 20: ...splay change user registers Z Boot First Available Device Z 1 Boot from Floppy Drive 0 Z 2 Boot from SCSI Unit 0 Z 3 Boot from GIDE Master S Setup DS 1302 RAM Parameters T Display Date Time T S Set Date Time L Load OS First Available and return to DEBUG L 1 Load from Floppy Drive 0 L 2 Load from SCSI Unit 0 L 3 Load from GIDE Master The input line editor includes support for Tab tabstops are fixed...
Page 21: ...ints should only be set on the first op code byte of a machine instruction Setting them elsewhere will have undefined consequences 5 3 Display Set Memory The command format is D addr length If a length is given the indicated number of bytes is rounded up to the next multiple of 16 and the memory contents are displayed 16 bytes to a lines thus D 500 27 0500 69 6E 20 49 6E 74 65 6C 2D 68 65 78 20 66...
Page 22: ... one instruction to be executed before control returns to the debugger If a count is entered that number of instructions will be executed before the debugger regains control After each instruction is executed the resulting register values are displayed as for the Display Set Registers command below Caution Tracing under the N command runs the target program much slower than real time execution The...
Page 23: ... Loading Files The debugger can read and store files in Intel hex format This facility is limited to storing in RAM the debugger cannot program the flash ROM Typically the debugger is connected to a PC running a suitable terminal emulator program and the text upload facility of that program is used to transfer the file There is no facility for altering the stored addresses data is stored as specif...
Page 24: ...rameter of 1 will start a boot from the first floppy drive referred to as drive 0 A parameter of 2 will start a boot from device 0 on an attached SCSI interface A parameter of 3 will start a boot from a GIDE type IDE interface Simply typing Z will attempt a boot from each of the three devices Floppy SCSI and GIDE in that order If the floppy boot fails it will attempt a SCSI boot If that fails a GI...
Page 25: ...second SRAM parts are necessary in order to use zero additional mem ory wait states 70 nanosecond parts are provided in the kit so it s okay to pick 0 Default is 2 additional wait states C Additional I O Waits The IO controller chip requires at least two additional wait states Unpredictable IO errors will result if fewer than two are used Default is 3 additional wait states D Console Data Rate Spe...
Page 26: ...rd can support homebrewed SCSI and IDE ATA interfaces Chips can be salvaged from SCSI interfaces for other machines and installed onto a board for the P112 The GIDE interface does not use a salvaged controller chip but instead uses programmable logic chips These interfaces however are beyond the current scope of this manual Default is 7 for the GIDE IDE ATA interface H I and J Logical Hard Drive S...
Page 27: ...s will show a regular signature on the CRO Be aware that the Z80182 drives the M1 line differently to the Z 80 it is only active on interrupt acknowledge cycles 6 2 Garbaged Sign on Message That message is the result of a lot of power on self testing so errors in it can tell you a lot If it identifies the SMC chip then the basic interface to that chip is OK this has not tested interrupts or DMA Th...
Page 28: ...0B ie ld ix 0BH This will always work Insert the system disk and execute G The system will attempt to read the boot sector When the debugger regains control display the registers If the read was successful HL will contain 8400H ie it will advance past the buffer and the carry bit Bit 0 of F will be zero After an error carry will be set and A will contain the error code thus calerr equ 1 Error in a...
Page 29: ...ide Bits 1 0 Selected drive Byte 2 Bit 7 Did not see TC at end of sector This is normal in this system Bit 6 Unused Bit 5 CRC error Bit 4 DMA under overrun Bit 3 Unused Bit 2 No data seen Bit 1 Write Protect Bit 0 Missing address mark 6 4 An Example One board worked on everything except booting the system Running the above disk test gave a DMA underrun error A continuity checker showed a missed jo...
Page 30: ...ve a much reduced set of divisors available and will normally require a carefully chosen clock frequency The boot software can recognise and adjust to the following clocks 12 288MHz 16 0MHz 18 432MHz 24 576MHz The last two will require a faster CPU chip to be fitted The Z80182 includes several in built peripheral functions All these are fully supported by the Z80 vectored interrupt system The foll...
Page 31: ...the FDC requires TEND asserted during the DMA cycle addressed to it not to the memory Consequently the FDC is programmed not to use TENDx which implies that all transfers will post a end of cylinder error This is allowed for by the software 7 1 4 Memory Mapping The Z80182 includes two levels of memory mapping logic The first maps the 64kB logical address space into a maximum of 3 zones in the 1MB ...
Page 32: ...the ROM and RAM 1 sites This permits a pre programmed ROM to be fitted in RAM 1 U3 to program a blank flash device in U4 See section 10 2 7 2 1 ROM The ROM socket U4 can accept a 32kB flash ROM part The board includes facilities for in system programming of 5V and 12V flash ROMs For normal use the header P12 should be jumpered across Pins 2 3 WE For 12V parts Intel or AMD 28F256 the 12V regulator ...
Page 33: ...rs and similar devices Of course the 32kB may be extended by a bank switching arrangement on the expansion board Expansion board memory should be selected when the signals ROMCS and RAMCS are both high ie no on board memory is selected The read and write enables are MRD and MWR which enable bus transactions If necessary the WAIT line may be driven low to delay the CPU 7 3 IO Cycle Control The mult...
Page 34: ...IO chip occupies the IO address space 80 BF These addresses are mapped to appear to the IO chip as standard PC addresses Programming of the multi IO features follows standard PC practice The address mapping is described below 7 6 2 Cycle Timing The IO chip latches address data at the beginning of IOR or IOW This can cause problems with the Zilog timing which regards the RD and WR signals as basica...
Page 35: ...o logically swap Drives 0 and 1 This assumes the drives have the DS1 jumper set as is normal for PC AT usage Given this Drive 0 connects directly to the PCB with no ribbon cable cores swapped This is to enable the PCB to be mounted directly on the disk drive with the PCB and drive connectors adjacent Drive 1 will be the further away and will have cores 10 16 swapped in the cable It should be noted...
Page 36: ...7C651 FDC37C652 FDC37C665 FDC37C666 The 651 and 665 are fully software configurable However the 652 and 666 have some functions configured by external resistors These are not otherwise fitted and are the only surface mount resistors on the board Space limitations preclude putting reference designators on the board however they are all 1206 size 27k parts Their reference designators are R101 R111 N...
Page 37: ...ed the voltage converter U12 and its associated components may be omitted 8 4 Realtime Clock A Dallas DS1302 realtime clock RAM is used This has a serial interface which is implemented using 3 spare parallel port pins from the CPU chip Be aware that this chip when first powered up defaults to write protected and oscillator disabled Before it will run normally you must first turn off write protect ...
Page 38: ...ent 1 Diskette controller request 2 DMA request 0 to CPU 3 Expansion socket request 4 DMA request 1 to CPU 5 SIO request This header selects the sources for DMA requests The Z180 core includes 2 DMA channels which may be connected among 3 possible sources diskette expansion socket and serial IO channel The standard boot code requires Pins 1 and 2 jumpered 9 3 P3 Flash Bootload Selector Pin Assigme...
Page 39: ...FF0 The ROM code will be copied into U3 RAM overwriting the Debugger workspace and the CPU will then halt Without removing power hold the Reset input pin low Then interchange the J3 jumpers and fit the new ROM in U4 do this carefully you are hot plugging the ROM Finally remove the Reset The board will reboot and will report RAM at 40000 47FFF physical The code now sees logical ad dresses 0000 7FFF...
Page 40: ...rt can support synchronous modes in which the CPU s SYNC pin normally used as the RI input becomes an output To pre vent contention with the RS232 receiver the jumper at P5 should be removed in synchronous working The Z180 uses the CTS and DCD pins as hardware enables For the port to operate these must either be strapped to the DTR output or connected via for example a null modem cable to another ...
Page 41: ... remains the same if reversed The reset input is intended for a switch to ground It may be left open The board will automatically reset when powered up 9 7 P7 Parallel Printer Pin Assigment 1 Strobe 2 AutoFeed 3 D0 4 Error 5 D1 6 Init 7 D2 8 Select In 9 D3 10 Ground 11 D4 12 Ground 13 D5 14 Ground 15 D6 16 Ground 17 D7 18 Ground 19 Ack 20 Ground 21 Busy 22 Ground 23 PaperEnd 24 Ground 25 Select 26...
Page 42: ...printer interface The interface offers basic bidirectional capability expanded ECP EPP fea tures are not available 9 8 P8 Serial Port 2 Pin Assigment 1 DCD in 2 RXD in 3 TXD out 4 DTR out 5 Ground 6 DSR in 7 RTS out 8 CTS in 9 RI in 10 Not used Pin 1 is at the top left when holding the board with the battery to the bottom right See P4 for details This port is implemented on the combination IO chip...
Page 43: ...tom right All odd numbered pins are Ground Drive wiring is the usual PC AT type with lines 10 16 switched around between the drives The Drive 0 and 1 signals are logically interchanged within the IO chip so that the drive connected without a twist in the cable is Drive 0 This will typically be the drive on which the board is mounted 9 10 P10 Disk Drives 2 and 3 Same as P9 but decodes Drives 2 and ...
Page 44: ...er to MWR or to Vdd For normal use connect to MWR 9 13 P13 RAM Pin 30 Function Pin Assigment 1 5V 2 U2 and U3 pin 30 3 A17 For 512kB RAM chips this pin should connect to A17 For smaller parts connect to Vdd 9 14 P14 Extra Serial Ports Pin Signal 1 TXA1 2 RXA0 3 RTS0 4 CTS0 5 RTSB TEND1 6 DTRB 7 CTS1 8 TXA0 9 RXA1 10 DCD0 11 CTSB 12 DCDB 13 Vcc 14 TXDB 15 TRXCB 16 RXDB 17 RTXCB 18 SYNCB 19 GND 20 G...
Page 45: ... The signal names follow those used in the Z80182 data book which should be consulted for the capabilities of these ports The 3 ports are designated by the final characters in the names thus 0 1 Basic asynchronous ports B Full function a sycnhronous port Note that RTSB and TEND1 share a pin Either role is possible by suitably programming the CPU chip The standard software does not use this pin at ...
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Page 47: ...8C A5 9A A6 9B RAMCS 9C A7 10A Mem Read 10B Mem Write 10C Ground 11A M1 11B WAIT input to CPU 11C RD 12A IORQ 12B ROMCS 12C WR 13A RST reset 13B E 13C INT0 dedicated interrupt 14A TEND0 DMA Ch 0 End signal 14B TEND1 DMA Ch 1 End signal 14C IEI daisy chain interrupt enable in 15A EXTRQ Z 80 vectored interrupt 15B PHI main CPU clock 15C IEO daisy chain out 16A 5V 16B Ground 16C Ground 47 ...
Page 48: ...connected on the CPU card It is assigned for use by expansion cards to enable the daisy chain to be propagated through a maximum of two expansion cards The method is shown below J2 IE0 IE1 LOGIC IE0 IE1 LOGIC PLUG PLUG PLUG 15C 14C 15C 14C 15C 14C J1 J1 IE1 J2 Each expansion board has 2 jumpers J1 and J2 It may be seen that by setting these jumpers as shown a daisy chain of up to two vectored inte...
Page 49: ... provided For lack of room on the boot disk a seperate source code disk is provided as an image file on the documentation CD This necessarily requires a two drive system but since a one drive system is mostly useless for real work this isn t much of a burden ZSDOS commands are roughly similar to MSDOS If you re familiar with straight CP M you should be able to jump right in All the usual commands ...
Page 50: ...is sort of command is the same used to switch drives in MSDOS In fact that s exactly how one changes drives in ZSDOS and CP M Just type B to switch to drive B 10 2 Flash Programmer The application used for programming flash chips for the 1996 run of P112 boards was written for DOSPLUS and does not yet work under ZSDOS Please don t fool around with it unless you really know what you re doing and yo...
Page 51: ...this warranty excludes all others express or implied and defines our complete liability This warranty and the associated contract of purchase shall be governed by the laws of the State of California This board and its accompanying software are not designed or intended for use in safety critical or life support applications No liability of any kind is accepted for such use See also the file LICENSE...
Page 52: ...on The designer of the P112 Dave Brooks has a website on the P112 at http members iinet net au daveb p112 p112 html A new website specifically for this release of the P112 is at http www cs csubak edu dgriffi proj p112 and is mirrored at http anachronda homeunix com 8000 p112 Griffith Consulting 2108 Sandy Lane Bakersfield CA 93306 URL http www cs csubak edu dgriffi proj p112 Email dgriffi cs csub...
