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Dave Embedded Systems Axel ULite, Hardware Manual

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AXEL ULite Hardware Manual

v.1.0.2

3.7

Power consumption

This section will be completed in a future version of this manual.

3.8

CPU module connectors

All interface signals 

AXEL ULite

 provides are routed through SODIMM 

DDR3 204 pin (named J2). The dedicated carrier board must mount the 
mating connector and connect the desired peripheral interfaces 
according to 

AXEL ULite

 pinout specifications.

For mechanical information, please refer to Section 4 (Mechanical 
specifications). For pinout and peripherals information, please refer to 
Sections 5 (Pinout table) and 6 (Peripheral interfaces).

August, 2019

23/65

Summary of Contents for Axel ULite

Page 1: ...www dave eu info dave eu ARM Cortex A7 MPCore CPU Module Lite Line HARDWARE MANUAL DAVE Embedded Systems AXEL ULite...

Page 2: ...AXEL ULite Hardware Manual v 1 0 2 Page intentionally left blank August 2019 2 65...

Page 3: ...R3 memory bank 18 3 2 1 Reliable Storage Strategy 19 3 2 1 1 Write endurance 20 3 3 NOR flash bank 21 3 4 NAND flash bank 22 3 5 Memory map 22 3 6 Power supply unit 22 3 7 Power consumption 23 3 8 CPU...

Page 4: ...6 47 6 4 8 UART 7 48 6 4 9 UART 8 for wires 48 6 4 10 I C3 48 6 4 11 I C4 48 6 4 12 ECSPI2 48 6 4 13 ECSPI3 49 6 4 14 MMC SD SDIO2 49 6 5 Customized pin muxing configuration 50 7 Power reset and contr...

Page 5: ...Fig 7 Accessing the RESERVED AREA 63 Index of Tables Tab 1 Related documents 9 Tab 2 Abbreviations and acronyms used in this manual 9 Tab 3 CPU Memories Buses 14 Tab 4 Peripherals 14 Tab 5 Electrical...

Page 6: ...AXEL ULite Hardware Manual v 1 0 2 August 2019 6 65...

Page 7: ...are not designed for use in life support appliances devices or systems where malfunction of these products can reasonably be expected to result in personal injury DAVE Embedded Systems customers who...

Page 8: ...requests can be sent to support axel dave eu Software upgrades are available for download in the restricted access download area of DAVE Embedded Systems web site http www dave eu reserved area An ac...

Page 9: ...Abbreviation Definition BTN Button EMAC Ethernet Media Access Controller GPI General purpose input GPIO General purpose input and output GPO General purpose output PCB Printed circuit board PMIC Powe...

Page 10: ...v 1 0 2 Revision History Version Date Notes 0 0 1 June 2016 First draft PRELIMINARY 0 9 0 August 2016 First Release 1 0 0 September 2016 Release 1 0 1 December 2018 Minor fixes 1 0 2 August 2019 Mino...

Page 11: ...ing and power consumption thanks to the ARM Cortex A7 architecture Additionally the use of this processor enables extensive system level differentiation of new applications in many industry fields whe...

Page 12: ...oftware full compatibility High flexibility with up to 4 different scalable CPU versions Base General Purpose Security Advanced security thanks to TRNG Crypto Engine etc Embedded IoT connectivity vers...

Page 13: ...Fig 2 AXEL ULite block diagram AXEL ULite Hardware Manual v 1 0 2 2 2 Block Diagram August 2019 13 65...

Page 14: ...zes on request Tab 3 CPU Memories Buses Feature Specifications Options LAN Ethernet 10 100 Mbps PHY on board additional MII RMII interface Video Input up to 1x CSI port 24 bit parallel Video Output up...

Page 15: ...50 mm x 25 40 mm Operating temperature range Commercial 0 C 70 C Temperature Range Industrial 40 C 85 C Temperature Range Extended 40 C 105 C Temperature Range Weight 6 4 g Connectors SODIMM 204 pin...

Page 16: ...XP i MX6UL application processor The i MX6UL processors feature NXP s advanced implementation of the ARM Cortex A7 MPCore which operates at speeds up to 528MHz These SOCs include a deep encryption and...

Page 17: ...ring 128KB unified L2 cache NEON MPE co processor External memories interconnect Connectivity peripherals including 2xRMII Ethernet 10 100 interfaces SD SDIO MMC Serial buses USB UART I C SPI CAN On G...

Page 18: ...M memory bank is composed by 16 bit width chip The following table reports the SDRAM specifications Dimension Value CPU connection Multi mode DDR controller MMDC Size min 256 MB Size max 512 GB Width...

Page 19: ...lash memory and thereby to reduce cost per bit and increase maximum chip capacity so that flash memory could compete with magnetic storage devices like hard disks Because of the series connection and...

Page 20: ...ND 5 000 to 10 000 for medium capacity applications 1 000 to 3 000 for high capacity applications Samsung K9G8G08U0M Example for medium capacity applications TLC NAND 1 000 Samsung 840 SLC floating ga...

Page 21: ...is connected to the eCSPI channel 1 Specific models of the AXEL ULite SOM provide the SPI NOR as boot memory The following table reports the NOR flash specifications Dimension Value CPU connection EC...

Page 22: ...SLC Bootable Yes Tab 10 NAND flash specifications 3 5 Memory map For detailed information please refer to chapter 2 Memory Maps of the i MX Applications Processor Reference Manual 3 6 Power supply un...

Page 23: ...uted through SODIMM DDR3 204 pin named J2 The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to AXEL ULite pinout specifications For me...

Page 24: ...hapter describes the mechanical characteristics of the AXEL ULite SOM Mechanical drawings are available in DXF format on request 4 1 Board Layout The following figures shows the physical dimensions of...

Page 25: ...figure shows the AXEL ULite connectors layout The following table reports connectors specifications Part number Standard SO DIMM 204 pin DDR3 Mating connectors DDR3 SO DIMM SOCKET Part number TE Conne...

Page 26: ...ll dimensions on the following table are in millimeters Dimension Value Width 67 60 mm Depth 25 40 mm Max components height top side 1 35 mm Max components height bottom side 1 2 mm PCB height 1 086 1...

Page 27: ...AXEL ULite components CPU x pin connected to CPU pad named x PMIC x pin connected to the Power Manager IC LAN x pin connected to the LAN PHY Ball pin Component ball pin number connected to signal Tab...

Page 28: ...U SNVS_TAMPER9 R6 J2 51 CSI_PIXCLK CPU CSI_PIXCLK E5 J2 53 CSI_MCLK CPU CSI_MCLK F5 J2 55 PMIC_VSNVS PMIC VSNVS 34 J2 57 DGND DGND J2 59 VPWR PMIC VPWR 31 J2 61 VLDO2 PMIC VLDO2 15 J2 63 VLDO2 PMIC VL...

Page 29: ...Not connected Leave this pin floating J2 127 GPIO1_IO06 CPU GPIO_IO06 K17 Internally connected to ethernet PHY MDIO J2 129 GPIO1_IO07 CPU GPIO_IO07 L16 Internally connected to ethernet PHY MDC J2 131...

Page 30: ...cted Leave this pin floating J2 169 N C Not connected Leave this pin floating J2 171 N C Not connected Leave this pin floating J2 173 N C Not connected Leave this pin floating J2 175 DGND DGND J2 177...

Page 31: ...AXEL ULite Hardware Manual v 1 0 2 Tab 13 J2 odd pins 1 to 203 August 2019 31 65...

Page 32: ...PU BOOT_MODE1 U10 Reset_scheme_ AXEL ULite J2 28 GPIO1_IO08 CPU GPIO_IO08 N17 Reset_scheme_ AXEL ULite Handling_CPU initiated_software_res et J2 30 DGND DGND J2 32 CPU_PMIC_STBY_R EQ CPU CCM_PMIC_STBY...

Page 33: ...J2 86 NAND_CLE CPU NAND_CLE A4 Internally connected to NAND flash J2 88 NAND_ALE CPU NAND_ALE B4 Internally connected to NAND flash J2 90 NAND_RE CPU NAND_RE D8 Internally connected to NAND flash J2 9...

Page 34: ...CPU LCD_DATA01 A9 J2 138 LCD_DATA02 CPU LCD_DATA02 E10 J2 140 LCD_DATA03 CPU LCD_DATA03 D10 J2 142 LCD_DATA04 CPU LCD_DATA04 C10 J2 144 LCD_DATA05 CPU LCD_DATA05 B10 J2 146 DGND J2 148 LCD_DATA06 CPU...

Page 35: ...B_OTG1_VBUS CPU USB_OTG1_VBUS T12 J2 190 DGND DGND J2 192 N C Not connected Leave this pin floating J2 194 USB_OTG1_CHD CPU USB_OTG1_CHD U16 J2 196 USB_OTG2_DN CPU USB_OTG2_DN T13 J2 198 USB_OTG2_DP C...

Page 36: ...change the pin configuration In section 6 1 are described the HW configurations of those peripherals that can not change position such us ethernet USBs etc In section 6 2 are described the peripherals...

Page 37: ...1 1 Ethernet On board Ethernet PHY Micrel KSZ8019RN provides interface signals required to implement the 10 100 Mbps Ethernet port The transceiver is connected to the triple speed Ethernet MAC ENET mo...

Page 38: ...ng table describes the interface signals Pin Name Pin Internal Connections Ball pin USB_OTG1_VBUS J2 188 CPU USB_OTG1_VBUS T12 USB_OTG1_CHD J2 194 CPU USB_OTG1_CHD U16 USB_OTG1_DP J2 200 CPU USB_OTG1_...

Page 39: ...75 CPU SD1_DATA0 B3 SD1_DATA1 J2 77 CPU SD1_DATA1 B2 SD1_DATA2 J2 79 CPU SD1_DATA2 B1 SD1_DATA3 J2 81 CPU SD1_DATA3 A2 Tab 18 SD1 interface signals The others SD1 pins like SD1_CD SD1_WP etc are multi...

Page 40: ...are Manual v 1 0 2 transfers 32 bit wide by 64 entry FIFO for both transmit and receive data Configurable Polarity and phase of the Chip Select SS and SPI Clock SCLK Direct Memory Access DMA support A...

Page 41: ...e on board bootable NAND Flash is interfaced with the i MX6UL through the NAND controller port on chip select 0 For further details please refer to Section 3 4 The following table describes the interf...

Page 42: ...red as either inputs or outputs for connections to external devices In addition the GPIO peripheral can produce CORE interrupts The device contains 5 GPIO blocks and each GPIO block is made up to 32 i...

Page 43: ...4x4 matrix keypad ethernet controller for remote connection Ethernet on Invariant base up to four UARTs for interfacing to the actuators to be controlled synchronous audio interface SAI for external c...

Page 44: ...D_DATA08 J2 152 CPU LCD_DATA09 B11 LCD_DATA09 J2 154 CPU LCD_DATA10 A11 LCD_DATA10 J2 156 CPU LCD_DATA11 E12 LCD_DATA11 J2 158 CPU LCD_DATA12 D12 LCD_DATA12 J2 160 CPU LCD_DATA13 C12 LCD_DATA13 J2 162...

Page 45: ...Pin Internal Connections Ball pin I2C2_SCL J2 38 CPU GPIO1_IO00 K13 I2C2_SDA J2 48 CPU GPIO1_IO01 L15 6 3 4 KPP The following table describes the interface signals Pin Name Pin Internal Connections B...

Page 46: ...H14 UART2_CTS J2 181 CPU UART2_CTS J15 6 3 7 UART3 Pin Name Pin Internal Connections Ball pin UART3_TX_DATA J2 191 CPU UART3_TX_DATA H17 UART3_RX_DATA J2 193 CPU UART3_RX_DATA H16 UART3_CTS J2 195 CP...

Page 47: ...ration list that configure the system as an IoT Gateway Remember that some standard peripherals in the list above are required to configure your system This configuration suppose to use enet1 eth1 eth...

Page 48: ...ENET2_RX_ER J2 103 CPU ENET_RX_ER D16 ENET2_TX_EN J2 105 CPU ENET_TX_EN B15 ENET2_TX_DATA1 J2 107 CPU ENET_TDATA1 A16 ENET_MDIO J2 127 CPU GPIO_IO06 K17 ENET_MDC J2 129 CPU GPIO_IO07 L16 6 4 2 UART1 P...

Page 49: ...Pin Name Pin Internal Connections Ball pin UART4_RX_DATA J2 124 CPU LCD_DATA_EN B8 UART4_CTS J2 126 CPU LCD_RESET E9 UART4_RTS J2 128 CPU LCD_VSYNC C9 UART4_TX_DATA J2 130 CPU LCD_HSYNC D9 6 4 6 UART...

Page 50: ...C14 UART8_RX_DATA J2 180 CPU LCD_DATA21 B14 UART8_CTS J2 142 CPU UART8_CTS C10 UART8_RTS J2 144 CPU UART8_RTS B10 6 4 10 I C3 Pin Name Pin Internal Connections Ball pin I2C3_SDA J2 134 CPU LCD_DATA00...

Page 51: ...CS1 B5 6 4 14 MMC SD SDIO2 If an external eMMC is required it can be mapped on the following pin list instead of using internal NAND Pin Name Pin Internal Connections Ball pin SD2_RESET J2 88 CPU NAND...

Page 52: ...ng the DAVE Embedded Systems sales department at sales dave eu Please contact your sales representative for assistance on pin multiplexing design Additionally for Evaluation Kit owners is available on...

Page 53: ...supply voltage range is 3 3 4 5V please note that this range can be widened by the use of an external MOSFET for more details please refer to technical support 3 power supply voltage range is 3 25 3...

Page 54: ...als reading of this page is highly recommended For information about power consumption please refer to this article 7 1 Power Supply Unit PSU and recommended power up sequence Implementing correct pow...

Page 55: ...ement circuitry that completes PMIC functionalities The PSU generates the proper power up sequence required by i MX processor and surrounding memories and peripherals synchronizes the powering up of c...

Page 56: ...ence as per I MX6 UL requirements 7 SOM_PGOOD signal is set ti logic 1 this active high signal indicates that SoM s I O is powered This signal can be used to manage carrier board power up sequence in...

Page 57: ...ons 7 2 1 CPU_PORn The following devices can assert this active low signal PMIC voltage monitor this device monitors critical power voltages and triggers a reset pulse in case any of these exhibits a...

Page 58: ...ons During the inception of the AXEL ULite product specific attention has been addressed to find a viable trade off to satisfy such requirements This effort has led to the options that are detailed in...

Page 59: ...lf The following paragraphs introduce the available options For further information please refer to DAVE Embedded Systems Developers Wiki or contact the Technical Support Team 7 5 1 JTAG Recovery JTAG...

Page 60: ...7 6 Multiplexing Most of the i MX6UL processor pins have multiple signal options These signal to pin and pin to signal options are selected by the input output multiplexer called IOMUX The IOMUX enabl...

Page 61: ...oretical maximum power consumption value would be useless for the majority of system designers building their application upon AXEL ULite module because in most cases this would lead to an over sized...

Page 62: ...unit and to implement thermal management properly 8 2 1 Configuration1 This section will be completed in a future version of this manual 8 3 Heat Dissipation This section will be completed in a future...

Page 63: ...L ULite Hardware Manual v 1 0 2 9 Application Notes Please refer to the following documents available on DAVE Embedded Systems Developers Wiki Document Location Tab 22 Application Notes August 2019 63...

Page 64: ...the development kit please contact sales dave eu for further details send the product information to the sales department sales dave eu the sales department will create the account and enable access...

Page 65: ...AXEL ULite Hardware Manual v 1 0 2 Fig 7 Accessing the RESERVED AREA August 2019 65 65...

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