CIRCUIT DESCRIPTION
6-2
Part No. 001-4090-101/102
6.2.4 TRANSMIT & RECEIVE DATA
Transmit Data from the RS-232 port is level-shifted to TTL by U15 and passed through the CPU for
further processing and conversion from asynchronous to synchronous format. The CPLD modem, U16, takes the
digital data stream from SIO-A of the CPU and synthesizes to the constant-amplitude analog baseband signal. The
synthesized data stream is filtered by U10, buffered by U9B, and applied to radio module TXA at P1-6.
Received signals are applied to the RXA pin on P1-13 and amplified by U3A. U3A gain is set by the
electronic potentiometer, U5D, and filtered by U10. The same filter circuit is used for transmission and reception.
Two analog multiplexer/demultiplexer gates (U8A and B) controlled by TX_EN line are used for sharing. The
filter U10 cut-off frequency is programmable by the CPLD, based on the data rate. The analog signal is buffered
by U1D and fed to Peak Detectors U3C, U3D, and U3B, and to slicer circuit U1C via U1B. The raw data is passed
to the CPLD modem (U16) for de-scrambling and receive clock recovery. The resulting synchronous bit stream is
fed to CPU SIO-A for further processing and conversion to asynchronous format before delivery to the RS-232
driver and to the user port.
6.2.5 INTEGRA-H A/D AND DIGIPOT
An 8 channel, 8-bit successive approximation A/D converter, type ADC0838 (U4), is interfaced to CPU
(U17) and Peripheral (U21).
CH0 and CH1 are connected to the positive and negative peak detector of the modem section. The
software can read the positive or negative value of an RX signal, or using the differential mode, the actual peak-to-
peak RX signal value.
CH3 is used to measure the radio RSSI signal which was amplified by U7A.
CH4 is connected to the radio diagnostic signal (P3-14). This pin is used to output an analog signal
corresponding to the power output and the reflected signal.
CH5 is connected to U6 (LM50), a temperature sensor with a -40 to +125°C range.
CH6 is used to read the SWB+ voltage after proper scaling into the 0-5 V range.
CH7 and CH8 are connected to EXT SIGNAL 1 and 2. A 2:1 divider and protection circuit is inserted
between both external signals and the A/D.
The External Signal (pins 1 and 2) is also connected to U21 at PB6 and PB7 through transistors Q3 and Q4
and can be used for Analog Input or Digital Output.
EXT_SIGNAL 2 is also connected to the Rx test point RX-TP through U8A (74HC4066). Under software
control, the RX-TP (scaled down by 2) is available on the power connector for trouble-shooting purposes.
A 4-channel digital potentiometer type (U5) is used to adjust the RX Signal, TX Modulation, Carrier
Frequency and Carrier Detect Threshold.
