Data Translation DT9840 Series, User Manual

Page: 68 / 130

Chapter 2
68
Output Pulse Width and Duty Cycle Equations
The following equations relate to the output pulse width and duty cycle:
#clks per output pulse = FFF 1 – pulse_reg
For example, if pulse_reg = FFFFFFFEh, two clocks occur for each output pulse. In this
example, the output is active for counts FFFFFFFFh and 0.
Output pulse width = (#clks per output pulse) x (clock period)
For example, if the clock period is 55.55 ns and two clock occur for each output pulse, then the
output pulse width is 111.11 ns.
Output duty cycle = (output pulse width) / (output period)
For example, if the output pulse width is 222.2 ns and the output pulse period is 333.3 ns, then
the output duty cycle is 0.66 (66%).
Pulse_reg = FFF 1 – (duty cycle x (clock frequency /output frequency))
For example, if the clock frequency is 18 MHz, the output frequency is 6.0 MHz, and the
desired duty cycle is 2/3 (66%), then the required pulse_reg is FFFFFFFEh.
Counter Initialization
To initialize a counter/timer subsystem for continuous incrementing, do the following:
1. Select logic low for the gate source using the User Control registers, described in Table 13
on page 63 .
2. Select the desired mode, output polarity and clock source using the User Control
registers, described in
Table 13 on page 63 .
3. Load the User Period registers, described in Table 12 on page 62 , with the desired value.
4. Load the User Pulse registers, described in Table 12 on page 62 , with the desired value.
Once loaded, the user counter/timer is waiting for an active gate to begin counting.
5. Select the desired gate using the User Control registers, described in Table 13 on page 63 .
If logic high is selected as the gate source, the counter/timer begins counting immediately. If an
external gate is selected as the gate source, the counter counts when the external gate is active.
To initialize a counter/timer subsystem for an externally triggered one-shot operation, do the
following:
1. Select logic low for the gate source using the User Control registers, described in Table 13
on page 63 .
2. Select the desired mode, output polarity, and clock source using the User Control
registers, described in
Table 13 on page 63 .
3. Load the User Period registers, described in Table 12 on page 62 , with the desired value.
4. Load the User Pulse registers, described in Table 12 on page 62 , with the desired value.