Data Translation DT9840 Series, User Manual

Page: 67 / 130

Register Description
67
Count Sequence
The period register contains the initial count for the counter. When the host writes to the
period register, the value written is immediately loaded into the counter. When the user
counter counts, the counter increments from the initial count to the terminal count. When it
reaches the terminal count, the counter is reloaded with the initial count. The terminal count is
defined as 0. Therefore, the counter counts from period_reg to FFFFFFFFh, rolls over to 0, and
then reloads to period_reg.
Event Counting Equations
When the user counter is used to count events, load the period register with a value from 1 to
FFFFFFFFh. Use the following formula to determine the number of events that occurred:
# events = ctr – period_reg
where ctr is the value read from the counter. For example, if reading the counter returns a
value of 4, and period_reg = 1, three events occurred.
Output Period/Frequency Equations
When the user counter is used to generate an output signal, load the period register with a
value from 1 to FFFFFFFFh. The following equations relate to the output period and
frequency:
#clks per output period = FFF 2 – period_reg
For example, if period_reg = FFFFFFFEh, three clocks occur for each output period. In this
example, the counter counts FFFFFFFEh, FFFFFFFFh, 0, FFFFFFFEh, FFFFFFFFh, 0, and so on.
output period = (# clks per output period) x (clock period)
For example, if three clocks occur for each output period and the clock period is 55.555 ns,
then the output period is 166.666 ns.
output frequency = 1 / output period
For example, if the output period is 166.666 ns, then the output frequency is 6.0 MHz.
Period_reg = FFF 2 – (clock frequency / output frequency)
For example, if the clock frequency is 18 MHz and the desired output frequency is 6.0 MHz,
the required period_reg is FFFFFFFEh.