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Data Translation DT9840 Series, User Manual

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Data Translation DT9840 Series User Manual Download Page 65

Register Description

65

Counter/Timer Operation Modes

The following software-selectable modes are provided for each user counter/timer:

•

Retriggerable one-shot

 – In retriggerable one-shot mode, an external gate rising or falling 

edge, or a transition from software logic low to software logic high can be used to trigger 
a pulse output signal. 

When the gate is active, the counter begins incrementing. When the counter increments to 
the value specified in the pulse register, the user output is activated. The user output stays 
active until the counter increments to the terminal count. 

The user output is then deactivated and the counter is automatically reloaded with the 
initial count, which is specified in the period register. The user output then stays inactive, 
and the counter stays disabled, until the next active gate signal. Note that all gates that 
occur while the counter is incrementing are ignored. The active polarity of the user output 
is software-selectable.

4

User Counter 0 Measure Enable Flag
This signal indicates whether user counter/timer 0 
is enabled to perform a measurement. This bit 
resets to 0 on power up or counter/timer reset.

0 = Measure Disabled
1 = Measure Enabled
This bit is set when the host writes 1 to the 
user measure trigger enable command bit of 
the control register. This bit is cleared by the 
core at the completion of the measurement. It 
is also cleared when the host writes 0 to the 
user measure trigger enable command bit of 
the control register. 

R

5

User Counter 1 Measure Enable Flag
This signal indicates whether user counter/timer 1 
is enabled to perform a measurement. This bit 
resets to 0 on power up or counter/timer reset.

0 = Measure Disabled
1 = Measure Enabled
This bit is set when the host writes 1 to the 
user measure trigger enable command bit of 
the control register. This bit is cleared by the 
core at the completion of the measurement. It 
is also cleared when the host writes 0 to the 
user measure trigger enable command bit of 
the control register. 

R

6

User Counter 2 Measure Enable Flag
This signal indicates whether user counter/timer 2 
is enabled to perform a measurement. This bit 
resets to 0 on power up or counter/timer reset.

0 = Measure Disabled
1 = Measure Enabled
This bit is set when the host writes 1 to the 
user measure trigger enable command bit of 
the control register. This bit is cleared by the 
core at the completion of the measurement. It 
is also cleared when the host writes 0 to the 
user measure trigger enable command bit of 
the control register. 

R

7

Reserved

 –

 –

31:
8

Reserved

 –

 –

Table 14: User Status Register (Address 0xB000C030)  (cont.)

Bit

Register Description

Value

Type

Summary of Contents for DT9840 Series

Page 1: ...DT9840 Series UM 19197 T User s Manual Title Page ...

Page 2: ... its use No license is granted by implication or otherwise under any patent rights of Data Translation Inc Use duplication or disclosure by the United States Government is subject to restrictions as set forth in subparagraph c 1 ii of the Rights in Technical Data and Computer software clause at 48 C F R 252 227 7013 or in subparagraph c 2 of the Commercial Computer Software Registered Rights claus...

Page 3: ...tions to this equipment not expressly approved by Data Translation could void your authority to operate the equipment under Part 15 of the FCC Rules Note This product was verified to meet FCC requirements under test conditions that included use of shielded cables and connectors between system components It is important that you use shielded cables and connectors to reduce the possibility of causin...

Page 4: ......

Page 5: ...841 DT9841E and DT9841 VIB External Clock 16 DT9842 2 and DT9842 8 External Clock 16 Scalable Bus Master Clock 16 Operation Modes 17 Single Value Operations 17 Single Scan Operations 17 Multiple Scan Input Operations 18 Function Generator Output Operations 18 Continuous Loop Operations 18 Scan Loop Operations 19 Block Loop Operations 19 List Loop Operations 19 Triggers 20 Scalable Bus 21 LEDs 22 A...

Page 6: ...lly Cascaded Clock 31 Gate Types 32 Edge Types 33 Pulse Output Parameters 34 Polarity 34 Period Count 35 Pulse Width Count 35 Counter Timer Operation Modes 36 Standard Counting 36 Measure 38 Continuous Measure 39 Up Down Counting 41 One Shot 42 Repetitive One Shot 43 Chapter 2 Register Description 45 USB Bus DSP Hardware Interface 47 Calibration and Setup 51 Setting Up the Xicor Potentiometers 52 ...

Page 7: ...ns 84 Analog Output Specifications 87 Digital Input Specifications 88 Digital Output Specifications 89 Counter Timer Specifications 90 External Clock Specifications 91 External Trigger Specifications 92 Power Physical and Environmental Specifications 93 Regulatory Specifications 94 Connector Specifications 95 External Power Supply Specifications 97 Appendix B Connector Pin Assignments 99 DT9841 DT...

Page 8: ... J6 Pin Assignments 114 Connector J11 Pin Assignments 114 Screw Terminal Block TB2 Assignments 114 Screw Terminal Block TB3 Assignments 115 Sleek Box Front Panel 116 Connector J1 Pin Assignments 117 Connector J2 Pin Assignments 118 Connector J19 Pin Assignments 119 EP358E Accessory Panel 120 Connector J202 Pin Assignments 120 Connector J201 Pin Assignments 122 Index 125 ...

Page 9: ... the features of the analog input analog output digital I O and counter timer subsystems Chapter 2 Register Description describes all the registers that are used to program the DT9840 Series modules Chapter 3 Calibration describes the DT9841 Calibration Utility Appendix A Specifications lists the specifications of the module Appendix B Connector Pin Assignments shows the pin assignments for the co...

Page 10: ...nicates with the DSP program running on the DT9840 Series module Documentation for Code Composer StudioTM Integrated Development Environment IDE from Texas Instruments Documentation for Texas Instruments TMS320C6713 DSP processor Microsoft Windows XP Windows Vista or Windows 7 documentation Microsoft Visual Studio documentation USB 1 1 and USB 2 0 specifications on the USB web site http www usb or...

Page 11: ...11 1 Principles of Operation System Features 14 Analog Input Features 23 Analog Output Features 26 Digital I O Features 29 Counter Timer Features 30 ...

Page 12: ...s the operation of the DT9840 Series modules from a hardware perspective Figure 1 shows a block diagram of the DT9840 Series hardware architecture to frame the discussion in this chapter Note that bold entries indicate signals you can access For more detailed register level information refer to Chapter 2 starting on page 45 Table 1 DT9840 Series Modules Models Analog Inputs Converter Type Resoluti...

Page 13: ...tion Interface 16 Bit HPI Address Data 8 Ch Data A D Clock D A Serial Data 4 Control INT 6 A D Done Reset Rd_Wr_L HINT_L A D and D A Data JTAG 16 bit Scalable Bus 16 bit Scalable Bus INT 4 occurs with A D Trig Ctr Over Dig Change SB Done or A D or D A Error Serial Port 1 McBSP INT 5 D A Ready INT 7 SB FIFO Control Logic The DT9841 and DT9841 VIB features 8 24 bit A Ds and 2 24 bit DACs The DT9841E...

Page 14: ...ted Manual This allows the DSP program to run automatically each time the DT9840 Series module is powered on autonomously from the PC If desired you can also copy a user data fie into flash memory using the DT9840 Series Flash Download Utility By copying a user data into flash you can ensure that valuable information such as configuration information or collected data persists across power cycles ...

Page 15: ...e resulting signal from the oscillator is then divided by 2 to provide a clock signal to the A D and D A converters that is oversampled 256 times and has a 50 duty cycle For example if you specify an internal clock frequency of 100 kHz internally the module sets the oscillator to 51 2 MHz then divides the resulting signal by 2 to provide a 25 6 MHz signal with a 50 duty cycle to the A D and D A co...

Page 16: ...ce the external clock is started the DT9841 DT9841E and DT9841 VIB modules require 37 clock pulses before the first conversion is completed at 100 kHz this delay is 370 μs Thereafter the data is converted without delay at 100 kHz sampling occurs every 10 μs This initial delay is required by the filtering algorithms of the A D and D A converters DT9842 2 and DT9842 8 External Clock Because the DT98...

Page 17: ...cquires one input scan record and or outputs one output scan record on the next pulse of the sample clock and then stops Triggers are ignored An input scan record consists of the following information Eight analog input values corresponding to analog input channels 0 1 2 3 4 5 6 and 7 For the DT9841 DT9841E and DT9841 VIB these are 24 bit values for the DT9842 these are 16 bit values Note The DT98...

Page 18: ... a buffer that contains a specified number of output scan records Refer to page 17 for more information on output scan records The module continuously outputs the data in the output scan records from the buffer in memory to the analog output channels and or digital output lines on each pulse of the sample clock Once the operation is started the DSP is not used When you are finished outputting the ...

Page 19: ...Each input block consists of the following information Input scan records refer to page 17 for more information on input scan records The number of scans in each block A flag that indicates whether or not the block is full A pointer to the next block Each output block consists of the following information Output scan records refer to page 17 for more information on output scan records The number o...

Page 20: ...ules connect the external trigger to the Ext Trig BNC on the module This trigger asserts EXT_INT4 for processing Note If you are using the Scalable Bus to connect multiple modules and you want to externally trigger the master and slave modules at the same time you must supply an external trigger signal to the master and each slave module using external wiring The external trigger signals is not pr...

Page 21: ... the master clock source or to communicate with multiple modules that are operating asynchronously from each other The modules connect together using EP342 cables and the 50 pin Scalable Bus connectors J12 and J13 Refer to the DT9840 Series Getting Started Manual for more information on connecting modules using the Scalable Bus connectors Using the DT9840 Series Control Panel application you must ...

Page 22: ...communication operations on the Scalable Bus using software Return the address of slave modules Determine whether the module is ready for data transfer Allocate and deallocate buffers for data transfer Initiate transfer requests from the slave Transfer data and messages from the master to the slave LEDs LED CR6 on the DT9841E module and LED CR1 on the back of all other DT9840 Series modules is a t...

Page 23: ...ed on the clock rate These filters remove aliasing which is a condition where high frequency input components erroneously appear as lower frequencies after sampling The DT9842 2 and DT9842 8 use successive approximation converters no filtering is supported Using software you can configure the DT9841 and DT9841E modules to use 1 kΩ bias return termination resistance between the low side of each dif...

Page 24: ...e DT9842 2 and DT9842 8 modules use twos complement data encoding The data is 32 bit wide and left justified the right 16 bits are filled with zeros Note When the module is above range the value FFFFh plus full scale is returned When the module is below range the value 0000h minus full scale is returned You can use software to convert a twos complement code into voltage DC DC Coupling AC DC 4mA BN...

Page 25: ...board digital signal processing All samples must be read from the FIFO before the next A D conversion is done Error Conditions DT9840 Series modules report an overrun error if the data from the previous A D conversion is not read by the DSP or host computer before a new A D conversion occurs The DSP or host computer must clear this error To avoid this error ensure that the host program reads data ...

Page 26: ...on the clock rate to reduce noise On the DT9842 2 and DT9842 8 these analog output channels use successive approximation DACs no filtering is supported Within each DAC the digital data is double buffered to prevent spurious outputs before it is output as an analog signal Both DACs power up to a value of 0 V 10 mV Resetting the module does not clear the values in the DACs Refer to the DT9840 Series...

Page 27: ...ou can use software to convert a voltage value into a twos complement code Data Transfer The module packs 32 bits into each transfer The board generates an interrupt EXT_INT5 after the data in the analog output channel has been output For 100 kHz operation both analog output channels must then be updated with the next value to write within 10 μs For the DT9841 DT9841E and DT9841 VIB modules analog...

Page 28: ...er if the analog output data is not transferred fast enough within 10 μs of the fastest clock rate from the host computer to the module The host computer must clear this error To avoid this error ensure that the host computer provides analog output data to the module faster than the DACs are converting the data ...

Page 29: ...digital input the DT9840 Series module can generate an interrupt when any of the lines of port 0 changes state This feature is useful when you want to monitor critical signals or when you want to signal the host computer to transfer data to or from the module You specify an interrupt handler using software The DT9840 Series modules provide deglitching circuitry that you can enable using software f...

Page 30: ... input signal and outputs a clock output signal also called a pulse output signal as shown in Figure 4 Figure 4 Counter Timer Channel C T Clock Sources The following clock sources are available for each of the user counter timers Internal C T clock External C T clock Internally cascaded clock You specify the clock source to use for the selected counter timer using software Refer to the following s...

Page 31: ...l from a specified counter timer to the clock output signal of the proceeding counter timer without externally connecting two counters together For example if you specify a cascaded clock source for counter timer 2 the clock input of counter timer 2 is internally connected to the clock output of counter timer 1 The C T clock input source for counter timer 1 can be an internal or external C T clock...

Page 32: ...ion on the transition from the high level to the low level falling edge For up down counting mode increments the counter when the external gate signal is high and decrements the counter when the external gate signal is low Refer to page 36 for more information on these modes Inverted external gate input For standard counting operations enables the operation when the external gate signal is low and...

Page 33: ...ternal gate input pin goes from high to low falling edge In continuous measure mode starts the measurement when the signal connected to the external gate input goes from high to low falling edge the measurement stops on the next falling edge of the gate signal Rising edge external clock input In measure mode starts or stops the measurement when the signal connected to the external C T clock input ...

Page 34: ...ts the pin assignments of connector J17 on the module that correspond to the pulse output signals You can specify the following pulse width parameters using software Polarity described below Period count described on page 35 Pulse width count described on page 35 Polarity You can specify one of the following values for the polarity of the pulse output signal Active high low to high transitions The...

Page 35: ...FFFFFFh 0 FFFFFFFEh FFFFFFFFh 0 and so on output period clks per output period x clock period For example if three clocks occur for each output period and the clock period is 55 555 ns then the output period is 166 666 ns output frequency 1 output period For example if the output period is 166 666 ns then the output frequency is 6 0 MHz Pulse Width Count The pulse width count determines when the o...

Page 36: ...xternal C T clock when the enabled gate signal software external normal or external inverted is active Refer to page 31 for more information on the external C T clock source refer to page 32 for more information on gate types Since each counter timer is 32 bits you can count from 1 to FFFFFFFFh events before the counter rolls over to 0 and starts counting again You can read the value of the counte...

Page 37: ...l using the pulse width count Refer to page 34 for more information on the pulse output parameters The pulse output is activated when the counter increments to the pulse width count The pulse output stays active until the counter rolls over to 0 the terminal count The pulse output is then deactivated and the counter is automatically reloaded with the period count This sequence is repeated as long ...

Page 38: ... mode operation is complete or not using software When the operation is complete you can read the value of the counter Use the following equations to determine the frequency period and pulse width of the signal Frequency 18 MHz Number of Counts Period 1 Frequency Pulse width Number of Counts 18 MHz Note In measure mode the internal C T clock is used to calculate the interval of the signal between ...

Page 39: ...the specified start edge the counter begins incrementing The counter stops incrementing when it detects the next start edge The stop edge is ignored When the operation completes the counter remains idle until it is read On the next read the current value of the counter from the previous measurement is returned and the next measurement is started automatically Note If you read the counter before th...

Page 40: ...ample of Continuous Measure Mode Measuring the Frequency Time A D Value Counter Timer Value Status of Continuous Measure Mode Operation 10 5002 0 Operation started when the C T subsystem was configured but is not complete 20 5004 0 Operation not complete 30 5003 0 Operation not complete 40 5002 12373 Operation complete 50 5000 0 Next operation started but is not complete 60 5002 0 Operation not co...

Page 41: ...tays within the range of the counter since the operation is not be reliable if the counter increments above FFFFFFFh or decrements below 0 You can read the value of the counter at any time using software To use this mode specify an external C T clock source and either a normal or inverted external gate type Refer to page 31 for more information on the external C T clock source refer to page 32 for...

Page 42: ...e period count described on page 35 The pulse output then stays inactive and the counter stays disabled All subsequent clock and gate signals are ignored You can specify the polarity of the output signal refer to page 34 for more information In one shot mode the internal C T clock source is more useful than an external C T clock source Refer to page 30 for more information on the internal C T cloc...

Page 43: ...e counter is automatically reloaded with the period count described on page 35 The output then stays inactive and the counter stays disabled until the operation is re enabled with the proper gate signal All gate signals that occur while the counter is incrementing are ignored You can specify the polarity of the output signal refer to page 34 for more information In repetitive one shot mode the int...

Page 44: ...Chapter 1 44 ...

Page 45: ...gister Description USB Bus DSP Hardware Interface 47 Calibration and Setup 51 Analog Input Subsystem 56 Analog Output Subsystem 59 Digital I O Subsystem 61 Counter Timer Subsystem 62 Memory 70 Scalable Bus 72 ...

Page 46: ...escribes the registers that are used to program the DT9840 Series modules Note that the following designations are used for the register types R Read W Write R W Read and Write All addresses discussed are in hexadecimal notation ...

Page 47: ...t set this bit or bit 29 to 0 0 No external trigger occurred R W 3 For the DT9841 DT9841E and DT9841 VIB indicates whether turbo mode is selected for the A D and D A subsystems For the DT9842 2 and DT9842 8 this bit is reserved 1 Enables turbo mode for the A D and D A subsystems The maximum clock rate is the same at 51 2 MHz for 200 kHz throughput The accuracy degrades to 12 bits above 0 5 Nyquist...

Page 48: ...l port 0 changed state 1 The data of digital port 0 has changed 0 The data of digital port 0 has not changed R 14 Indicates whether interrupt EXT_INT4 is asserted by the external trigger 1 Enables the external trigger to assert EXT_INT4 0 Disables the assertion of EXT_INT4 by the external trigger R W 15 Reserved 0 R 16 Indicates whether to reset the A D and D A subsystems 1 Normal operation 0 Rese...

Page 49: ...he DSP reads the data This bit asserts EXT_INT6 0 A D conversions are not finished R W 27e Indicates whether an A D overrun error occurred 1 A D data was not read before the next conversion was completed interrupt EXT_INT4 is asserted This bit must be cleared set to 0 by the DSP or host Conversions do not stop however the data may be corrupt 0 A D data was read before the next conversion was compl...

Page 50: ...rted the LED turns orange When you download and run your DSP program this LED flashes green and orange When you download and run your DSP program this LED flashes green and orange If the downloaded program stops running this LED turns stops flashing in either the green or orange state to indicate that an error occurred and the debug LEDs CR7 to CR14 turn on You can define the state of the debug LE...

Page 51: ... is connected when 0 the USB cable is not connected R 18 DSP heartbeat signal readable by the USB interface without having to go through the host port interface This bit is toggled by the DSP program to indicate the program is running R W 19 Data input bit for the Xicor potentiometer see also bit 31 R 20 When 1 enables the chip that controls the A D 1 kΩ termination resistors see bits 26 and 27 Wh...

Page 52: ... port of the CY clock address 69h R W 30 Data output bit for the Xicor potentiometers see bit 31 When 1 the pin is in tristate so that the data can be read at bit 19 write to address 0xB000000C R W 31 Clocks the serial port of the Xicor Xicor X9258WS potentiometers that are used for calibrating the zero and full scale values of the A Ds and D As write to address 0xB000000C R W a All bits power up ...

Page 53: ...1 for a X9258 the addresses for the potentiometers are listed in Table 7 Table 7 Xicor Potentiometer Addresses and Functions Address Potentiometer Function 0000 0 A D 0 Zero Calibration 0000 1 A D 1 Zero Calibration 0000 2 A D 2 Zero Calibration 0000 3 A D 3 Zero Calibration 0001 0 A D 4 Zero Calibration 0001 1 A D 5 Zero Calibration 0001 2 A D 6 Zero Calibration 0001 3 A D 7 Zero Calibration 0010...

Page 54: ...meter Table 8 Xicor Potentiometer Instruction Set Instruction Instruction Format Operation I3 I2 I1 I0 P1 P0 R1 R0 Read WCR 1 0 0 1 1 0 1 0 N A N A Read the contents of the wiper counter register pointed to by P1 P0 Write WCR 1 0 1 0 1 0 1 0 N A N A Write new value to the wiper counter register pointed to by P1 P0 Read Data Register 1 0 1 1 1 0 1 0 1 0 1 0 Read the contents of the register pointed...

Page 55: ...crementing to decrease the output or decrementing to increase the output until the outputs equal 0 00000 V 0 0004 V Each step changes the output by 0 3 mV There are a total of 256 steps Refer to Table 7 on page 53 for the address of each potentiometer 3 Set the full scale by writing a code of 77FFFF00h on both DACs and adjusting the appropriate potentiometers for an output voltage of 9 37500 V To ...

Page 56: ...9 of the Calibration and Setup register described in Table 6 on page 51 When the external clock is selected conversion begin on the high to low transition after a rising edge of the internal CAL signal On the DT9841 and DT9841E any or all of the analog input low signals can be terminated with a 1 kΩ bias return resistor to the isolated analog common Bits 20 26 and 27 of the Calibration and Setup r...

Page 57: ...egister described in Table 5 on page 47 is set if the A D clock is set faster than the A D converter specification or if the data was not read fast enough by the DSP or host This error must be cleared by the DSP or host Table 9 describes the DMA address map Table 9 DMA Address Map Address Register Description Type 0xB0004000 A D Data 0 above physical memory read only R 0xB0004004 A D Data 1 R 0xB0...

Page 58: ...004020 Table 10 Flags at Address 0xB0004020 Bit Register Description 29 1 A D A trigger occurred 0 A D A trigger did not occur 30 1 An A D trigger error occurred 0 An A D trigger error did not occur 31 1 An A D trigger occurred 0 An A D trigger did not occur ...

Page 59: ...tion on the Scalable Bus The serial port is also used to reset and start the DACs The default mode is 128 times the sampling rate 0 dB attenuation DACs enabled mute disabled sharp roll off deemphasis disabled 8 times interpolation and 24 bit standard format For clock rates over 100 kHz the over sampling rate is 64 times On the DT9842 2 and DT9842 8 a system reset is used to initialize the DACs No ...

Page 60: ...es the D A data address map Table 11 D A Data Address Map Address Register Description Type 0xB0008000 D A Data 0 above physical memory W 0xB0008004 D A Data 1 above physical memory W 0xB0008008 Reserved zeros digital port 2a digital port 1 digital port 0 a For the DT9841 VIB module bit 0 of digital port 2 is used as the SCL clock and bit 1 of digital port 2 is used as the SDA data output the rema...

Page 61: ...e to digital port 1 only use register 0xB0010008 To read or write to digital port 2 only use register 0xB001000C Refer to Table 15 on page 70 for more information on these registers When port 0 is configured as an input port you can program the mask register located at address 0xB0010000 to generate an interrupt when any bit of port 0 changes state In this mode the sample rate changes to 1 MHz Ref...

Page 62: ...re 4 bytes of address space Register Description Type 0xB000C000b b Bits 31 to 0 are used to specify the period of the counter timer Data written to this location is stored in the period register and then immediately loaded into the counter timer Reads of this location return the current value of the counter timer This register and counter timer are set to 0 on power up or when the counter timer i...

Page 63: ...et up all the features characteristics of the counter before issuing this command 0 One shot triggers disabled 1 One shot triggers enabled W 9 8 User Aux Mode Select 1 0 These bits specify the auxiliary mode for the user counter timer They only matter if the mode select bits specify auxiliary mode These bits reset to 00 on power up or Counter Timer reset Bit 9 Bit8 0 0 Measure 0 1 Up down 1 0 Rese...

Page 64: ...the one shot pulse if the counter is in non retriggerable one shot mode It is also cleared when the user period register is loaded by the host R 1 User Counter 1 One Shot Trigger Enable Flag This flag indicates whether user counter 1 is enabled to detect one shot triggers This bit resets to 0 on power up or counter timer reset 0 One Shot Triggers Disabled 1 One Shot Triggers Enabled This bit is se...

Page 65: ...st writes 1 to the user measure trigger enable command bit of the control register This bit is cleared by the core at the completion of the measurement It is also cleared when the host writes 0 to the user measure trigger enable command bit of the control register R 5 User Counter 1 Measure Enable Flag This signal indicates whether user counter timer 1 is enabled to perform a measurement This bit ...

Page 66: ...wo signals Once the measure enable command is received from the host the counter increments from the time it detects the selected measure start edge until it detects the selected measure stop edge The counter then stops until it receives the next measure enable command from the host Continuous Measure Continuous measure mode uses the internal clock to measure the period of a signal on the external...

Page 67: ...xample if reading the counter returns a value of 4 and period_reg 1 three events occurred Output Period Frequency Equations When the user counter is used to generate an output signal load the period register with a value from 1 to FFFFFFFFh The following equations relate to the output period and frequency clks per output period FFFFFFFFh 2 period_reg For example if period_reg FFFFFFFEh three clock...

Page 68: ...sing the User Control registers described in Table 13 on page 63 2 Select the desired mode output polarity and clock source using the User Control registers described in Table 13 on page 63 3 Load the User Period registers described in Table 12 on page 62 with the desired value 4 Load the User Pulse registers described in Table 12 on page 62 with the desired value Once loaded the user counter time...

Page 69: ...egisters described in Table 13 on page 63 2 Select the desired mode output polarity and clock source using the User Control register described in Table 13 on page 63 3 Load the User Period registers described in Table 12 on page 62 with the desired value 4 Load the User Pulse registers described in Table 12 on page 62 with the desired value 5 Issue a one shot trigger enable command using the User ...

Page 70: ... lower 16 bits R 0xB0004000 A D Data Channel 0 Left Justified Data R 0xB0004004 A D Data Channel 1 Left Justified Data R 0xB0004008 A D Data Channel 2 Left Justified Data R 0xB000400C A D Data Channel 3 Left Justified Data R 0xB0004010 A D Data Channel 4 Left Justified Data R 0xB0004014 A D Data Channel 5 Left Justified Data R 0xB0004018 A D Data Channel 6 Left Justified Data R 0xB000401C A D Data...

Page 71: ...Register CE2 20 ns set up for 2 cycles W 0xA0000004 16 Bit SB Data Register CE2 20 ns ECLKIN 2 R a Refer to the DT9840 Series DSP Library User s Manual for more information on the CDB file b For the DT9841 VIB module bit 0 of digital port 2 is used as the SCL clock and bit 1 of digital port 2 is used as the SDA data output the remaining bits 2 7 of digital port 2 are reserved See page 51 for more ...

Page 72: ...y one time When it requests a transfer the slave module asserts interrupt EXT_INT4 The master module then reads each slave at a time to determine which module asserted the interrupt line The requesting slave module determines the size of the data that is transferred The module that is being written to indicates when the transfer operation is complete When the Scalable Bus is idle the master module...

Page 73: ... position M is the master and positions 1 and 2 are turned on as needed to represent the slave address The intensity of the LEDs for the addressed module is brighter than the LEDs for the nonaddressed modules The Scalable Bus is not supported by the DT9841E Table 17 SB Transfer Control Register Address 0xB0014004 Bit Register Name Register Description Type 0 Transfer Request 1 Valid only for slave...

Page 74: ...only on the master module The direction of the transfer that the slave requested is from the master to the slave 0 The direction of the transfer that the slave requested is from the slave to the master R 2 23 Transfer Count Valid only on the master module The size of the transfer that the slave requested to make to or from the master R 24 Ready Line Status 1 Module is ready to continue with a tran...

Page 75: ...s are written the FIFO half full flag on the addressed slave asserts interrupt EXT_INT7 for a 512 sample transfer to memory using DMA channel 7 When the module address is removed indicating that the transfer is done the slave module checks the FIFO not empty flag to complete the data transfer W 0xA0000004 Read Data Address Once the Enable bit is set the selected slave can write to the master throu...

Page 76: ...Chapter 2 76 ...

Page 77: ...77 3 Calibration Using the DT9841 Calibration Utility 79 Calibrating the Analog Input Subsystem 80 Calibrating the Analog Output Subsystem 82 ...

Page 78: ...circuitry on the DT9841 DT9841E and DT9841 VIB modules Note The DT9841 Calibration Utility is not supported by DT9842 2 and DT9842 8 modules This chapter describes how to calibrate the analog input and output subsystems of a DT9841 DT9841E or DT9841 VIB module using the DT9841 Calibration Utility ...

Page 79: ...1 Calibration Utility located under Start Programs Data Translation Inc DT9840 Series The main menu appears 2 Select the DT9841 DT9841E or DT9841 VIB module to calibrate and then click OK The firmware is downloaded to the module and the calibration utility starts after a few seconds Once the DT9841 Calibration Utility is running you can calibrate the analog input circuitry either automatically or ...

Page 80: ...nnels that you want to calibrate by clicking the checkboxes next to the channel numbers Each DT9841 channel must be calibrated separately 4 Click Start Auto Calibration You are prompted to verify that 0V is applied to the first selected channel 5 Connect a precision voltage source to the first selected analog input channel verify that 0 V is applied to the channel and then click OK The offset valu...

Page 81: ...st the offset as follows a Verify that 0 V is applied to the selected channel The current voltage reading for this channel is displayed in the A D Value window b Adjust the offset by entering values between 0 and 255 in the Offset edit box or by clicking the up down buttons until the A D Value is 0 000 V 4 Adjust the gain as follows a Verify that 9 375V is applied to the selected A D channel The c...

Page 82: ...x select 9 375 V 6 Adjust the gain by entering values between 0 and 255 in the DAC 0 Gain edit box or by clicking the up down buttons until the voltmeter reads 9 375 V 7 Connect an external precision voltmeter to Analog Output 1 DAC Ch1 of the DT9840 Series module 8 In the DAC Output Voltage box select 0 V 9 Adjust the offset by entering values between 0 and 255 in the DAC 1 Offset edit box or by ...

Page 83: ...Specifications 88 Digital Output Specifications 89 Counter Timer Specifications 90 External Clock Specifications 91 External Trigger Specifications 92 Power Physical and Environmental Specifications 93 Regulatory Specifications 94 Connector Specifications 95 External Power Supply Specifications 97 ...

Page 84: ... ended simultaneously sampled and held SSH Number of gains 1 the value is always 1 1 the value is always 1 Resolution 24 bits 16 bits Data encoding Twos complement Twos complement System accuracy full scale For DT9841 and DT9841E 0 024 For DT9841 VIB 0 044 0 02 Nonlinearity integral 4096 LSBs 0 01 Differential linearity monotonic 64 LSBs 1 LSB 1 LSB 1 192 μV 20 V 224 305 μV 20 V 216 Input signal r...

Page 85: ...ssive Approximation Group delay DT9841 DT9841E and DT9841 VIB 370 μs 100 kHz 37 Throughput Pass band 0 453 x Throughput Stop band 0 547 x Throughput Signal Noise Distortion 92 db 1 kHz 86 db 1 kHz Total Harmonic Distortion 96 db 1 kHz 90 db 1 kHz Spurious Free Dynamic Range 110 dB 90 dB Channel crosstalk 100 dB 1 kHz 100 dB 1 kHz Data Throughput Single channel Scan all channels 100 kS s For DT9841...

Page 86: ...uracy DT9841 VIB 1 0 IEPE Filter DT9841 VIB 2 pole Butterworth 10 kHz 3 dB a Cable capacitance of typically 30 pF per foot must be added Table 20 Analog Input Subsystem Specifications cont Feature DT9841 DT9841E and DT9841 VIB Specifications DT9842 2 and DT9842 8 Specifications ...

Page 87: ...2 5 V bipolar 10 V bipolar Throughput full scale 100 kHz 100 kHz Current output 5 mA minimum 10 V 2 kΩ 5 mA minimum 10 V 2 kΩ Output impedance 0 3 Ω typical 0 3 Ω typical Capacitive drive capability 0 001 μF minimum no oscillations 0 001 μF minimum no oscillations Protection Short circuit to analog common Short circuit to analog common Power on voltage 0 V 10 mV maximum 0 V 10 mV maximum Settling ...

Page 88: ... configured for digital input you can configure the software to interrupt the host computer whenever any of the bits changes state In addition to reduce noise and minimize false state changes you can enable a 10 ms deglitch function for port 0 when it is configured for digital input Termination 22 kΩ pull up series 22 Ω Input type HCT 5 V tolerant Yes Input load 22 kΩ pull up to 3 3 V Inputs Input...

Page 89: ...ions Number of lines For DT9841 VIB 16 Ports 0 and 1 each consisting of 8 programmable digital I O lines For all other DT9840 Series modules 24 Ports 0 1 and 2 each consisting of 8 programmable digital I O lines Termination 22 kΩ pull up series 22 Ω Outputs Output driver Output driver high voltage Output driver low voltage CMOS 22 kΩ pull up to 3 3 V 0 4 V 10 mA Back EMF diodes Yes ...

Page 90: ... voltage 5 V tolerant Minimum pulse width Maximum frequency HCT with 22 kΩ pull up to 3 3 V 2 4 V minimum 0 8 V maximum Yes 25 ns high 25 ns low 20 MHz Gate Inputs Input type High level input voltage Low level input voltage 5 V tolerant Minimum pulse width HCT with 22 kΩ pull up to 3 3 V 2 4 V minimum 0 8 V maximum Yes 25 ns high 25 ns low Counter Outputs Output driver high voltage Output driver l...

Page 91: ... Specifications Feature Specifications Input type HCT Rising Edge Sensitive with 22 kΩ pull up resistor High level input voltage 2 4 V minimum Low level input voltage 0 8 V maximum Minimum pulse width 9 ns high 9 ns low Maximum frequency DT9841 and DT9841E DT9842 2 and DT9842 8 51 2 MHza 100 kHz a For the DT9841 and DT9841E the conversion rate Clock frequency 512 ...

Page 92: ...ignal to the DT9840 Series modules Table 26 External Trigger Specifications Feature Specifications Input type HCT Rising Edge Sensitive with 22 kΩ pull up resistor High level input voltage 2 4 V minimum Low level input voltage 0 8 V maximum Minimum pulse width 50 ns high 50 ns low Maximum frequency 50 0 kHz ...

Page 93: ... All other DT9840 Series modules 5 A maximum 3 A typical DT9841 VIB 700 mA All other DT9840 Series modules 1 A maximum Physical Dimensions Board Level Version Sleek Box DT9841E 280 x 100 x 22 mm All other DT9840 Series modules 233 35 mm x 220 mm 229 mm L x 247 mm W x 114 mm H Weight Board Level Version Sleek Box DT9841E 0 492 lb 223 g All other DT9840 Series modules 1 572 lbs 713 g 5 85 lbs 2 654 ...

Page 94: ...ations Feature Specifications EMI FCC part 15 class A EN 55022 1994 based on CISPR 22 1993 EN 50082 1 1998 IEC 801 2 1984 IEC 801 3 IEC 801 4 VCCI Japan version of CISPR 22 Safety 8 KV air 4 KV contact 3 V m from 27 to 500 MHz 1 KV coupled to AC lines 0 5 KV coupled to I O lines UL CSA RoHS EU Directive 2002 95 EG Compliant as of July 1st 2006 ...

Page 95: ...e Bus J12 and J13 3M N10250 52E2VC 3M 10150 6000 Serial Port J4 AMP Tyco 747844 4 AMP Tyco 747904 2 5 V Power Input J11b Kycon KPJ 4S S Kycon KPP 4P USB J6 AMP 787780 2 Data Translation EP310 USB cable or AMP Tyco 1487588 1 DT9841 DT9842 2 DT9842 8 Board Level Version J2a J19 Hirose DF3 2P 2V20 Housing Hirose DF3 2S 2C Crimp pins 2 per Hirose DF3 2428SC J3 AMP Tyco 146130 6 Blackhawk JTAG emulator...

Page 96: ...s module or Sleek Box AMP Tyco 747904 2 AMP Tyco 747844 4 Connector that attaches to the EP335 cabled AMP Tyco 747905 7 Male 9 pin D sub connector of the EP335 cabled a The following fan is recommended for use with connector J2 Sunon model number KDE0505PFB3 8 or Data Translation part number 19372 b The following power supply is recommended Total Power International model number TPES49 05060KPP 4P...

Page 97: ...ly EP348 Specifications Feature Specifications Type Total Power medical power supply TPES49 05060KPP 4P Input voltage Typical 90 264 V AC Input current Typical 0 79 A at 115 V AC 0 37 A at 230 V AC Frequency 47 to 63 Hz Inrush current 32 A at 230 V AC Output voltage 5 V DC Output current 6 0 A Output wattage Typical 45 50 W Noise and ripple 1 peak to peak Regulatory specifications UL N CE FCC Clas...

Page 98: ...Appendix A 98 ...

Page 99: ...99 B Connector Pin Assignments DT9841 DT9842 2 and DT9842 8 Modules 100 DT9841E Module 109 Sleek Box Front Panel 116 EP358E Accessory Panel 120 ...

Page 100: ...odes of operation at bit rates of up to 33 Mbps Refer to the data sheet for the TMS320C6713 from Texas Instruments part number SPRS088F for more information on programming the serial port Connector J6 a 4 pin USB connector Refer to Table 34 on page 103 for more information on this connector Connector J11 a 4 pin locking connector provided for attaching an external 5 V power input signal Refer to T...

Page 101: ...n on this connector Note You can use the 2 position terminal block TB1 instead of connector J19 if you wish Screw terminal block TB1 is provided for attaching an external 5 V power output signal Refer to Table 40 on page 108 for more information on the screw terminal block assignments Note You can use connector J19 instead of screw terminal block TB1 if you wish Connector J2 Pin Assignments Table ...

Page 102: ...ies Getting Started Manual for connection information and to the DT9840 Series DSP Library User s Manual for information on the serial debugging functions If you want to program this serial port refer to the data sheet for the TMS320C6713 from Texas Instruments for more information Signal Description McBSP Pin McBSP Function McBSP Internal Pull Up or Pull Down 1 CLKS1 External Clock Source E1 Inpu...

Page 103: ...s not used USB connector is type B Red 2 USB_D White 3 USB_D Green 4 AGND1 Black Table 35 Power Input Connector J11 Pin Assignments Pin Signal Descriptiona a You must consider the wire size and length before connecting power to connector J11 The module requirement is 5 V 0 25 V at the connector with less than 50 mV pp of ripple The power supply must also be isolated from the computer or from the p...

Page 104: ...n 2 SB0b b These signals are driven by the transmitting module 1 SB0_Returnb 4 SB1b 3 SB1_Returnb 6 SB2b 5 SB2_Returnb 8 SB3b 7 SB3_Returnb 10 SB4b 9 SB4_Returnb 12 SB5b 11 SB5_Returnb 14 SB6b 13 SB6_Returnb 16 SB7 15 SB7_Returnb 18 SB8b 17 SB8_Returnb 20 SB9b 19 SB9_Returnb 22 SB10b 21 SB10_Returnb 24 SB11b 23 SB11_Returnb 26 SB12b 25 SB12_Returnb 28 SB13b 27 SB13_Returnb 30 SB14b 29 SB14_Returnb...

Page 105: ...Output 07a 61 Analog Output 07 Returna 26 External D A Triggerb 60 Isolated Digital Ground 25 External D A Clockb 59 Isolated Digital Ground 24 External A D Triggerb 58 Isolated Digital Ground 23 External A D Clockb 57 Isolated Digital Ground 22 Digital Input Triggerb 56 Isolated Digital Ground 21 Digital Input Clockb 55 Isolated Digital Ground 20 Digital Output Triggerb 54 Isolated Digital Ground...

Page 106: ...rnal Gate 2 Encoder B2b a Available on the DT9842 8 module only b Currently this function is not implemented Table 38 Analog Input Connector J18 Pin Assignments Pin Signal Description Pin Signal Description 34 Analog Input 00 68 Analog Input 00 Returna 33 Analog Input 01 67 Analog Input 01 Returna 32 Analog Input 02 66 Analog Input 02 Returna 31 Analog Input 03 65 Analog Input 03 Returna 30 Analog...

Page 107: ...d 43 Reserved 8 Reserved 42 Reserved 7 Reserved 41 Reserved 6 Reserved 40 Reserved 5 Reserved 39 Reserved 4 Reserved 38 Reserved 3 Reserved 37 Reserved 2 Amp Low 36 Analog Common 1 5 V Isolated Output 35 Isolated Power Ground a For the DT9842 2 and DT9842 8 which have single ended analog inputs these signals are analog grounds Table 39 Power Output Connector J19 Pin Assignments Pin Signal Descript...

Page 108: ... TB1 Assignments Table 40 lists the assignments of the power output screw terminal block TB1 Table 40 Power Output Screw Terminal Block TB1 Pin Signal Description 1 5 V Output 1 Aa a Fused at 1 A with a poly fuse 2 Isolated Power Ground ...

Page 109: ...hown in Table 44 on page 113 This serial port serial port 1 McBSP of the DSP can also be programmed for several modes of operation at bit rates of up to 33 Mbps Refer to the data sheet for the TMS320C6713 from Texas Instruments part number SPRS088F for more information on programming the serial port Connector J6 a 4 pin USB connector Refer to Table 45 on page 114 for more information on this conne...

Page 110: ...t 01 67 Analog Output 01 Return 32 Reserved 66 Reserved 31 Reserved 65 Reserved 30 Reserved 64 Reserved 29 Reserved 63 Reserved 28 Reserved 62 Reserved 27 Reserved 61 Reserved 26 External D A Triggera 60 Isolated Digital Ground 25 External D A Clocka 59 Isolated Digital Ground 24 External A D Triggerb 58 Isolated Digital Ground 23 External A D Clockc 57 Isolated Digital Ground 22 Digital Input Tri...

Page 111: ... Gate 1 Encoder B1a 2 User Clock Input 2 Encoder A2a 36 Isolated Digital Ground 1 User Counter Output 2 35 External Gate 2 Encoder B2a a Currently this function is not implemented b Use this pin to connect an external trigger to the DT9841E module c Use this pin to connect an external clock to the DT9841E module Table 42 Analog Input Connector J2 Pin Assignments on the DT9841E Pin Signal Descripti...

Page 112: ...rved 47 Reserved 12 Reserved 46 Reserved 11 Reserved 45 Reserved 10 Reserved 44 Reserved 9 Reserved 43 Reserved 8 Reserved 42 Reserved 7 Reserved 41 Reserved 6 Reserved 40 Reserved 5 Reserved 39 Reserved 4 Reserved 38 Reserved 3 Reserved 37 Reserved 2 Amp Low 36 Analog Common 1 5 V Isolated Output 35 Isolated Power Ground Table 42 Analog Input Connector J2 Pin Assignments on the DT9841E cont Pin S...

Page 113: ...DT9840 Series Getting Started Manual for connection information and to the DT9840 Series DSP Library User s Manual for information on the serial debugging functions If you want to program this serial port refer to the data sheet for the TMS320C6713 from Texas Instruments for more information Signal Description McBSP Pin McBSP Function McBSP Internal Pull Up or Pull Down 1 CLKS1 External Clock Sour...

Page 114: ...r is type B Red 2 USB_D White 3 USB_D Green 4 AGND1 Black Table 46 Power Input Connector J11 Pin Assignments on the DT9841E Pin Signal Descriptiona a You must consider the wire size and length before connecting power to connector J11 The module requirement is 5 V 0 25 V at the connector with less than 50 mV pp of ripple The power supply must also be isolated from the computer or from the power com...

Page 115: ...nts on the DT9841E Screw Terminal Signal Namea a These signals are provided for attaching an external 5 VDC 100 mA fan output signal The fan will turn on with an onboard temperature sensor if the DT9840 Series module exceeds 45 C If the module exceeds 60 C an interrupt is generated The following fan is recommended Sunon model number KDE0505PFB3 8GN or Data Translation part number 19372 1 Fan 2 Fan...

Page 116: ...to Table 49 on page 117 for more information on this connector Digital In Out Connector J2 A 37 pin connector provided for attaching digital I O signals Refer to Table 50 on page 118 for more information on this connector Counter Timer Connector J19 A 25 pin connector provided for attaching counter timer signals Refer to Table 51 on page 119 for more information on this connector Screw terminal bl...

Page 117: ...modules these signals are reserved 13 Analog Output 03a 14 Analog Output 04a 15 Analog Output 05a 16 Analog Output 06a 17 Analog Output 07a 18 Analog Common 19 Reserved 20 Analog Input 00 Returnb b For the DT9841 VIB DT9842 2 and DT9842 8 which have single ended analog inputs these signals are analog grounds 21 Analog Input 01 Returnb 22 Analog Input 02 Returnb 23 Analog Input 03 Returnb 24 Analog...

Page 118: ...not implemented 10 Digital In Out 2 Port 2a Encoder 2 Clrb 11 Digital In Out 1 Port 2a Encoder 1 Clrb 12 Digital In Out 0 Port 2a Encoder 0 Clrab 13 Isolated Digital Ground 14 Isolated Digital Ground 15 Isolated Digital Ground 16 Isolated Digital Ground 17 Isolated Digital Ground 18 Isolated Digital Ground 19 Reserved 20 Digital In Out 7 Port 0 21 Digital In Out 6 Port 0 22 Digital In Out 5 Port 0...

Page 119: ...tput 1 4 User Clock Input 1 Encoder A1a 5 User Counter Output 0 6 User Clock Input 0 Encoder A0a 7 Isolated Digital Ground 8 Isolated Digital Ground 9 Isolated Digital Ground 10 Isolated Digital Ground 11 Isolated Digital Ground 12 Isolated Digital Ground 13 Reserved 14 External Gate 2 Encoder B2a 15 Isolated Digital Ground 16 External Gate 1 Encoder B1a 17 Isolated Digital Ground 18 External Gate...

Page 120: ...des these connectors J202 Connector 68 pin connector for connecting the EP358E accessory panel to the J2 connector of the DT9841E module This connector brings out all the analog input signals from the module to the accessory panel J201 Connector 68 pin connector for connecting the EP358E accessory panel to the J1 connector of the DT9841E module This connector brings out all of the analog output di...

Page 121: ...eserved 42 Reserved 43 Reserved 44 Reserved 45 Reserved 46 Reserved 47 Reserved 48 Reserved 49 Reserved 50 Reserved 51 Reserved 52 Reserved 53 Reserved 54 Reserved 55 Reserved 56 Reserved 57 Reserved 58 Reserved 59 Reserved 60 Reserved 61 Reserved 62 Reserved 63 Reserved 64 Reserved 65 Reserved 66 Reserved 67 Analog Input 01 Return 68 Analog Input 00 Return Table 52 Pin Assignments for Connector J...

Page 122: ... Digital Output Clocka 20 Digital Output Triggera 21 Digital Input Clocka 22 Digital Input Triggera 23 External A D Clocka 24 External A D Triggera 25 External D A Clocka 26 External D A Triggera 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved 32 Reserved 33 Analog Output 01 34 Analog Output 00 35 External Gate 2 Encoder B2a 36 Isolated Digital Ground 37 External Gate 1 Encoder B1a 38 ...

Page 123: ...round 61 Reserved 62 Reserved 63 Reserved 64 Reserved 65 Reserved 66 Reserved 67 Analog Output 01 Return 68 Analog Output 00 Return a Currently not implemented Table 53 Pin Assignments for Connector J201 on the EP358E Accessory Panel Pin Signal Description Pin Signal Description ...

Page 124: ...Appendix B 124 ...

Page 125: ...nter timer ext trig ext clock connector DT9841E 110 B back panel of Sleek Box 116 BNC connectors analog input 116 120 analog output 116 120 external clock 101 116 120 external trigger 101 116 120 C calibrating the module 51 analog input subsystem 54 80 analog output subsystem 55 82 running the calibration utility 79 Calibration and Setup register 51 cascading counter timers 31 channels analog inpu...

Page 126: ... cascaded counter timer clock 31 external counter timer clock 31 internal C T clock 30 counter timer connector 116 120 Sleek Box 119 counter timer features 30 cascading internally 31 clock sources 30 edge types 33 gate types 32 operation modes 36 65 pulse output parameters 34 registers 62 specifications 90 units 30 counting events 36 CR1 LED 22 50 CR10 LED 22 50 CR11 LED 22 50 CR12 LED 22 50 CR13 ...

Page 127: ...f Sleek Box 116 function generator output 18 G gain analog input 24 analog output 26 gate types 32 inverted 32 logic high level 32 on software 32 H Hardware Control and Status register 47 high to low pulse output 34 I IEPE features 23 input range 24 internal clock 15 cascaded counter timer 31 counter timer 30 interrupts digital I O 29 J J1 connector pin assignments 109 116 120 DT9841E 110 Sleek Bo...

Page 128: ...34 M master module 21 measure mode 38 measuring frequency 38 39 measuring period 38 measuring pulse width 38 memory 14 70 Memory Space Address Map 70 module addresses 21 module specifications 93 94 95 multiple scan operation mode 18 N Nyquist Theorem 15 O one shot mode 42 operation modes 17 continuous block 19 continuous I O 18 continuous list 19 continuous measure 39 continuous scan 19 function g...

Page 129: ...l 63 User Status 64 Write Data Address 75 regulatory 94 repetitive one shot mode 43 resolution analog input 24 analog output 26 rising edge clock input 33 rising edge gate type 33 S sample clock 14 sample rate 19 SB Control register 72 SB Transfer Control register 73 SB Transfer Status register 74 Scalable Bus 72 connections 21 master clock 16 Scalable Bus connectors 100 116 Scalable Bus pin assig...

Page 130: ...screw terminal block DT9841E 109 114 TB3 screw terminal block DT9841E 110 115 transferring data analog input 25 analog output 27 trigger sources external 20 software 20 TTL trigger 20 U units counter timer 30 USB bus DSP hardware interface 47 USB connector 100 109 116 DT9841 103 DT9841E 114 DT9842 2 103 DT9842 8 103 User Control registers 63 User Status register 64 V voltage range 24 W Write Data ...

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