Data General AViiON Series, Customer Documentation

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Assigning VME Data Bus and Interrupt Priorities
E-3
014–001867
Highest – Slot 1 (Arbiter)
Slot 4
Slot 2
Slot 6
Slot 3
Lowest – Slot 5
Most Data General AViiON servers (except Models 400, 3000. 4000, and 4300 series)
use fixed prioritized arbitration.
Single–Level Bus Arbitration
In the single–level bus arbitration scheme, all boards on the VMEbus, including the
arbiter, are at fixed priority level 3. Priority for simple competing requests (for
example, two concurrent requests with no requests waiting) is based on the relative
position of the board with respect to the arbiter (the board closest to the arbiter has
the highest priority and thus gets the bus grant). Similarly, if two or more requests
are waiting when a requester releases the bus, the requesting board closest to the
arbiter gets the bus grant.
Data General AViiON server Models 400, 3000, 4000, and 4300 series use
single–level bus priority arbitration.
Performance Considerations
The standard DTB priority recommendations given in Chapter 1 provide a basic
approach that works in most systems. However, for optimum performance on some
large system configurations and with certain application programs, you may want to
try a different arrangement, either of the fixed DTB priorities or of the positioning of
boards within the system. Consider the following factors when evaluating and
reordering a system’s priority structure:
D
Is data lost if the device cannot gain access to the VMEbus when required?
D How much data can be buffered by the controller, or devices attached to the
controller, before system performance is affected by the device’s inability to gain
access to the bus?
D What is the average time a device holds the DTB bus once it has gained access?
D
How much of the available VMEbus bandwidth does a device require to make the
most efficient use of its time on the bus?
D Does the device have VME block transfer capabilities (refer to Motorola VMEbus
Specification)?
D Is the device a master or slave on the VMEbus when it is transferring data?
D Does the system’s physical constraints restrict board positioning on the VMEbus?
D Does a board create problems with other boards on the VMEbus? (Non–DGC
VMEbus controllers only)