NET-FRM01 Users Manual (Rev 1.3)
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http://www.daqsystem.com
2. NET-FRM01 Functions
2.1 Block Diagram
As shown in the following figure, main control of the board is performed in FPGA Core Logic.
The primary functions are receiving the frame data and are transmitting/receiving the UART data.
NET-FRM01
10/100/1000Mbps
Ethernet
Tranceiver
FPGA Core
Logic
DDR2
#1
DDR2
#2
M
D
R
I
26
Clock
Rx/Tx
RX0+/-
RX1+/-
Camera Link
Receiver
RX2+/-
Camera
/-
[Figure 2-1. NET-FRM01 Block Diagram]
Programming FPGA Core Logic is performed via the JTAG interface. The logic program of the
FPGA is saved in a flash ROM, it is located on the board and loaded at the power-up time.
