Dalsa Piranha ES Series, User Manual

Page: 26 / 106

Piranha ES-xx User Manual
03-032-20070-02 Teledyne DALSA
26
Camera Link Configuration
The Cam era Link interface is im p lem ented as a Base, Med iu m , or Fu ll Configu ration in
the Piranha ES cam eras d ep end ing on the m od el nu m ber and follow s the stand ard
Cam era Link configu ration.
Table 7: Camera Control Configuration
Signal Configuration
CC1 EXSYN C
CC2 Sp are
CC3 Forw ard
CC4 Sp are
See Ap p end ix B for the com p lete Cam era Link configu ration table . Also refer to the
Cam era Link Road m ap , available from the Know led ge Center on ou r w ebsite
here , for
m ore inform ation.
Input Signals, Camera Link
The cam era accep ts control inp u ts throu gh the Cam era Link MDR26F connector.
The camera ships in internal sync, internal programmed integration (exposure mode 7) TDI Mode.
EXSYNC (Triggers Frame Readout)
Fram e rate can be set internally u sing the ser ial interface. The external control signal
EXSYN C is op tional and enabled throu gh the serial interface. This cam era u ses the
falling
edge of EXSYN C to trigger p ixel read ou t. Section 3.3.5 Exp osu re Mod e and Line/ Fram e
Rate for d etails on how to set fram e tim es, exp osu re tim es, and cam era m od es.
Direction Control
You control the CCD shift d irection throu gh the serial interface. With the softw are
com m and ,
scd
, you d eterm ine w hether the d irection control is set via softw are control or
via the Cam era Link control signal on CC3. Refer to section 3.3.3 Setting the Cam era’s
CCD Shift Direction for d etails.
Output Signals, Camera Link
These signals ind icate w hen d ata is valid , allow ing you to clock the d ata from the cam era
to you r acqu isition system . These signals are p art of the Cam era Link configu ration and
you shou ld refer to the Cam era Link Road m ap , available from the Know led ge Center on
ou r w ebsite,
here , for the stand ard location of these signals.
Clocking Signal Indicates
LVAL (high) Ou tp u tting valid line
DVAL (high) Valid d ata
STROBE (rising ed ge) Valid d ata
FVAL (high) Ou tp u tting valid fram e

The cam era internally d igitizes 12 bits and ou tp u ts 8 MSB or all 12 bits d ep end ing on
the camera’s Camera Link operating mode. Refer to 3.4.2 Setting the Camera Link
Mod e for d etails.
IMPORTANT:
This camera’s data
should be sampled on
the rising edge of
STROBE.
i