DS3112
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9 HDLC
CONTROLLER
The DS3112 contains an on-board HDLC controller with 256-byte buffers in both the transmit and
receive paths. When the device is operated in the T3 mode, the HDLC controller is only active in the C-
Bit Parity mode. When the device is operated in the E3 mode, the user has the option to connect the
HDLC controller to the Sn bit position. On the receive side, the HDLC controller is always connected to
the receive E3 framer. If the host does not wish to use the HDLC controller for the Sn bit, then the status
updates provided by the HDLC controller are ignored. On the transmit side, the host selects the source of
the Sn via the E3SnC0 and E3SnC1 controls bits in the T3/E3 Control Register (Section
9.1 Receive Operation
On reset, the receive HDLC controller will flush the receive FIFO and begin searching for a new
incoming HDLC packet. The receive HDLC controller performs a bit by bit search for a HDLC packet
and when one is detected, it will zero destuff the incoming data stream and automatically byte align to it
and place the incoming bytes as they are received into the receive FIFO. The first byte of each packet is
marked in the receive FIFO by setting the Opening Byte (OBYTE) bit. Upon detecting a closing flag, the
device will check the 16-bit CRC to see if the packet is valid or not and then mark the last byte of the
packet in the receive FIFO by setting the Closing Byte (CBYTE) bit. The CRC is not passed to the
receive FIFO. When the CBYTE bit is set, the host can obtain the status of the incoming packet via the
Packet Status bits (PS0 and PS1). Incoming packets can be separated by a single flag or even by two flags
that share a common zero. If the receive FIFO ever fills beyond capacity, the new incoming packet data
will be discarded and the Receive FIFO Overrun (ROVR) status bit will be set. If such a scenario occurs,
then the last packet in the FIFO is suspect and should be discarded. When an overflow occurs, the receive
HDLC will stop accepting packets until either the FIFO is completely emptied or reset. If the receive
HDLC controller ever detects an incoming abort (seven or more ones in a row), it will set the Receive
Abort Sequence Detected (RABT) status bit. If an abort sequence is detected in the middle of an
incoming packet, then the receive HDLC controller will set the Packet Status bits accordingly.
The receive HDLC has been designed to minimize its real-time host support requirements. The receive
FIFO is 256 bytes, which is deep enough to store the three T3 packets (Path ID, Idle Signal ID, and Test
Signal ID) that can arrive once a second. Hence in T3 applications, the host only needs to access the
receive HDLC once a second to retrieve the three messages. The host will be notified when a new
message has begun (Receive Packet Start status bit) to be received and when a packet has completed
(Receive Packet End status bit). Also, the host can be notified when the FIFO has filled beyond a
programmable level called the high watermark. The host will read the incoming packet data out of the
receive FIFO a byte at a time. When the receive FIFO is empty, the REMPTY bit in the FIFO will be set.
9.2 Transmit Operation
On reset, the transmit HDLC controller will flush the transmit FIFO and transmit an abort followed by
either 7Eh or FFh (depends on the setting of the TFS control bit) continuously. The transmit HDLC then
waits until there are at least two bytes in the transmit FIFO before beginning to send the packet. The
transmit HDLC will automatically add an opening flag of 7Eh to the beginning of the packet and zero
stuff the outgoing data stream. When the transmit HDLC controller detects that the TMEND bit in the
transmit FIFO is set, it will automatically calculate and add in the 16-bit CRC checksum followed by a
closing flag of 7Eh. If the FIFO is empty, then it will begin sending either 7Eh or FFh continuously. If
there is some more data in the FIFO, then the transmit HDLC will automatically add in the opening flag
and begin sending the next packet. Between consecutive packets, there are always at least two flags of
7Eh. If the transmit FIFO ever empties when a packet is being sent (i.e., before the TMEND bit is set),
