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Figure 13-8. Intel Read Cycle (Multiplexed)
Address
Valid
Data Valid
CA[7:0]
CD[15:0]
CWR
CCS
CRD
t1
t2
t3
t4
t5
t10
CALE
t11
t12
t13
t14
t14
NOTE: t14 STARTS ON THE OCCURRENCE OF EITHER THE RISING EDGE OF CALE OR A VALID ADDRESS, WHICHEVER OCCURS FIRST.
Figure 13-9. Intel Write Cycle (Multiplexed)
CD[15:0]
CRD
CCS
CWR
t1
t2
t6
t4
t7
t8
t10
Address
Valid
CA[7:0]
CALE
t11
t12
t13
t14
t14
NOTE: t14 STARTS ON THE OCCURRENCE OF EITHER THE RISING EDGE OF CALE OR A VALID ADDRESS, WHICHEVER OCCURS FIRST.