DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
121 of 124
20.4.
Transmit AC Characteristics
AC CHARACTERISTICS—TRANSMIT SIDE
(V
DD
= 3.3V
±
5%, T
A
= 0°C to +70°C; for DS21354L;
V
DD
= 5.0V
±
5%
, T
A
= 0°C to +70°C for DS21554L;
V
DD
= 3.3V
±
5%, T
A
= -40°C to +85°C for DS21354LN;
V
DD
= 5.0V
±
5%
, T
A
= -40
°
C to +85
°
C for DS21554LN.)
(See
PARAMETER SYMBOL
MIN
TYP
MAX
UNITS
NOTES
TCLK Period
t
CP
488 ns
t
CH
75 ns
TCLK Pulse Width
t
CL
75
ns
TCLKI Period
t
LP
488 ns
t
LH
75 ns
TCLKI Pulse Width
t
LL
75
ns
t
SP
100
648
ns 1
t
SP
100
448
ns 2
t
SP
100
244
ns 3
TSYSCLK Period
t
SP
100
122
ns 4
t
SH
50
ns
TSYSCLK Pulse Width
t
SL
50
ns
TSYNC or TSSYNC Setup to TCLK
or TSYSCLK Falling
t
SU
20
t
CH
–5
or
t
SH
–5
ns
TSYNC or TSSYNC Pulse Width
t
PW
50 ns
TSER, TSIG, TDATA, TLINK,
TPOSI, TNEGI Setup to TCLK,
TSYSCLK, TCLKI Falling
t
SU
20
ns
TSER, TSIG, TDATA, TLINK,
TPOSI, TNEGI Hold from TCLK,
TSYSCLK, TCLKI Falling
t
HD
20 ns
TCLK, TCLKI, or TSYSCLK Rise
and Fall Times
t
R
, t
F
25
ns
Delay TCLKO to TPOSO, TNEGO
Valid
t
DD
50
ns
Delay TCLK to TESO Valid
t
D1
50
ns
Delay TCLK to TCHBLK, TCHCLK,
TSYNC, TLCLK
t
D2
50
ns
Delay TSYSCLK to TCHCLK,
TCHBLK, CO
t
D3
75
ns
CI Setup to TSYSCLK Rising
t
SC
20
ns
CI Pulse Width
t
WC
50 ns
Note 1:
TSYSCLK = 1.544MHz.
Note 2:
TSYSCLK = 2.048MHz.
Note 3:
TSYSCLK = 4.096MHz.
Note 4:
TSYSCLK = 8.192MHz.
