Daewoo DSI-9100, Service Manual

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CIRCUIT INFORMATION-MPEG
MemWait
Wait signal is produced in external device when accessing SRAM and peripheral devices. Wait signal is maintained as
Order status in the High status motivated by processor clock.
Not_OE
Read Strobe
ReadnotWrite
The ability to Read or Write of processing cycle.
Access cycle of EMI Bank3 and Bank2 is as following feature. The value of timing chart can be modified by the value of
Configuration Register setting.
Symbol Parameter Min Max Units Note
tCHAV Referecne Clock high to Address valid -8.0 0.0 ns
tCLSV Reference Clock low to Strobe valid -8.0 3.0 ns
tCHSV Reference Clock high to Strobe Valid -8.0 0.0 ns
tRCA/CH Read Data valid to Reference Clock high 13.0 ns
tCHRDX Read Data hold after Reference Clock high -2.0 ns
tSVRDX Read Data hold after Strobe valid 0.0 ns 1
tCLWOV Reference Clock low to Write Data valid -8.0 7.0 ns 1
tCHWOV Reference Clock high to Write Data valid -8.0 6.0 ns 1
tCHWDZ Reference Clock high to Write data tristate -8.0 6.0 ns
tCHRSV Reference Clock high to remaining Strobes valid -8.0 3.0 ns
tCHPH Reference Clock high to ProcClkOut high -8.0 0.0 ns
tWVCH MemWait valid to Reference Clock high 13.0 ns
tRVCH MemReq valid to Reference Clock high 13.0 ns
tRHWX MemWait hold after ProcClkOut high 0.0 ns 1
tPHRX Memreq hold after ProcClkOut high 0.0 ns 1
tPHEMIZ MemGrant to signals tristate when bus granted TBD ns 1
Chart 4. EMI Timing Value