Cypress S6J3200 Series, Manual

Page: 54 / 1355

CHAPTER 4:Block Diagram
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 53
1.
Block Diagram
Figure 1-1
MCUCONFIG Group
Debug Group - Coresight
Memory and Config
Core Group
64-Bit Multi-Layer AXI (HPM)
TCM
A
TCM
B
MPU D$
Cortex-R5F
I$
T
C
M
-6
4
TCM-64
3
2
B
it
S
in
g
le
-L
a
y
e
r
A
P
B
(
D
e
b
u
g
)
Debug I/F
ETM
SYSC0
Clock / Power /
Mode / State /
Timer /
LVDET / Wake-
Up / CSV / RTC/
HW-WDT / ext
IRQ
BootROM
AHB-64
Int Control
Timing
Protection
(TPU)
SWJ
3.3V IO
To Trace
Bus
PPU
AXI-64
AHB-32
AHB-32
APB-Selector
DAP
A
P
B
-3
2
Secure Bridge
TIC
Connection to
PERIPHERAL
Interrupt
signals from
Peripherals
TCM-
SRAM
Low Latency Peripheral Bus Matrix LLPBM
AXI-64 AXI-64
APB-32
Scratch
RAM
General
purpose
communicati
on
FP
AXI-64
SHE
AXI-64
AHB-64
DMAC
AXI-64
Backup
RAM_1
MFS 2 ch
RLT 2ch
EICU
M-CAN 2ch
M-CAN RAM
Common
PERI #0
M-CAN 2x
RLT 4x
BT 12x
FRT 8x
ICU 8x
OCU 8x
QPRC 0x
MFS 5x
AHB-32
AHB-32
APB-32
APPLPGR
P_SLAVE0
(APPS #5)
SG 4x
Common
PERI #1
RLT 4x
BT 12x
FRT 4x
ICU 4x
OCU 4x
QPRC 2x
MFS 5x
AHB-32
APB-32
APPLPGRP
_SLAVE1
(APPS #7)
ADC12B
SMC 6x
SMC_trg
LCDC
Common
PERI #2
RLT 4x
BT 0x
Port Config
CRC
PPU Master
GPIO / PPC /
PPU master /
RIC
DMAC
complex
AHB-32
AHB-32
Subsystem
Port
Mux
MPU
Traveo TM Platform
Flash Group
Pr ECC +
Security
DDRHS-SPI
1ch
Mem-Map
AHB-32
AHB-32
Backup
RAM_0
Always ON Domain (PD1) Backup RAM_0 (PD4_0)
Timer & Comm (PD6)
nested in PD1
Peripherals (PD2)
Power Domains
Backup RAM_1 (PD4_1)
MPU
HyperBus
Interface
LVDS
Format
CONV
APB-32
（
From Common Peri#0
）
Apps#4
AHB-32(PD1_Application)
・ PWM
・
LCDE
(APPS #4)
FPD_LINK
CONV
APB-32
AHB2APB
AHB-32
AHB-32
I2S0
MPU
MediaLB
Ethernet
MII MDIO
I2S1
PCM_PWM
AXI-64
MPU
Audio
DAC
AHB-32
WFG
MIXER
PRGCRC0
SOUND
SYSTEM_MOD
APPLGRP_MASTER
a
s
y
n
c
P
P
U
P
P
U
P
P
U
P
P
U
P
P
U
P
P
U
P
P
U
P
P
U
P
P
U
A
H
B
2
A
X
I
AXI-64
HyperBus
Interface
AXI-32
Apps#2 Apps#10
Apps#9
Apps#8
Apps#11 Apps#3
AXI-32
Apps#0,#1
EAM
AXI-64
5V IO
DDRHS-SPI
1ch
Mem-Map
PPU
AXI-32
HyperBus
Interface
SYSC1
State / Clock /
SW-WDT /
CSV (for PLL
and SSCG)
AHB-32
2.
Note
No description.