Cypress S6J3200 Series, Manual, Page: 356 / 1355

CHAPTER 15:12-/10-/8-bit Analog to Digital Converter
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 355
5.25.
A/D Converter Sampling Time Setting Registers (ADC12Bn_ST0 to
3)
ADC12Bn_ST0 to 3 registers specify four different settings for the selection of the sampling time of the
A/D converter. It is not allowed to update the value of these registers during A/D sampling operation
(ADC12Bn_TRGST0 to 1.TRGST and ADC12Bn_CHSTAT0 to 63.TRGST="1"). Only ADC12Bn_ST0
register is described here. Other registers (ADC12Bn_ST1, ADC12Bn_ST2 and ADC12Bn_ST3) have
similar bit fields.
REGISTER_NAME ADC12Bn_STi (i = 0 to 3)
OFFSET i*2
ACCESS_SIZE B H W
MULTIPLE 0:3
NUMERIC_TYPE
-
OTHER
-
A/D Converter Sampling Time Setting Register (ADC12Bn_ST0)
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME ST[15] ST[14] ST[13] ST[12] ST[11] ST[10] ST[9] ST[8]
ACCESS_TYPE R/W R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME ST[7] ST[6] ST[5] ST[4] ST[3] ST[2] ST[1] ST[0]
ACCESS_TYPE R/W R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE
INITIAL_VALUE 0 0 1 0 1 1 0 0
[bit15:0] ST[15:0] : A/D Converter Sampling Time Setting bits
These bits specify one of the four available settings for A/D converter sampling phase time.
This time is selected for a logical channel conversion by configuring the corresponding logical channel
register field ADC12Bn_CHCTRL0 to 63.SMTIME to "00".
Sampling time = ST value x Peripheral clock period
Do not set ST value below 6.
For specific values of minimum sampling time, please refer to the Device Data Sheet.