S6E2CC/C5/C4/C3/C2/C1 Series Flash Programming Specification, Document Number: 002-04913 Rev. *D
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1.4.8 FICLR (Flash Interrupt Clear Register)
This section explains FICLR.
This register is used to clear the interrupt state of Flash memory except DualFlash area.
bit
7
6
5
4
3
2
1
0
Field
Reserved
ERRIC
HNGIC
RDYIC
Attribute
RW
RW
RW
Initial value
0
0
0
[bit7:3] Reserved bits
The read values are undefined. Ignored on write.
[bit2] ERRIC : Flash ECC Error Interrupt Clear
This bit clears the ERR interrupt flag. By writing "1" to this bit, ERRIF bit of FISR register is cleared to "0".
Field
bit
Description
ERRIC
2
Flash ECC Error Interrupt Clear
At write
0: ECC error correction interrupt flag (ERRIF) is not changed.
1: ECC error correction interrupt flag (ERRIF) is cleared.
At read
"0" is read out.
[bit1] HNGIC : Flash HANG Interrupt Clear
This bit clears HNG interrupt flag. By writing "1" to this bit, HNGIF bit of FISR register is cleared to "0".
Field
bit
Description
HNGIC
1
Flash HANG Interrupt Clear
At write
0: Flash HANG interrupt flag (HNGIF) is not changed.
1: Flash HANG interrupt flag (HNGIF) is cleared.
At read
"0" is read out.
[bit0] RDYIC : Flash RDY Interrupt Clear
This bit clears RDY interrupt flag. By writing "1" to this bit, RDYIF bit of FISR register is cleared to "0".
Field
bit
Description
RDYIC
0
Flash RDY Interrupt Clear
At write
0: Flash RDY interrupt flag (RDYIF) is not changed.
1: Flash RDY interrupt flag (RDYIF) is cleared.
At read
"0" is read out.
