S6E2CC/C5/C4/C3/C2/C1 Series Flash Programming Specification, Document Number: 002-04913 Rev. *D
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1.4.2 FRWTR (Flash Read Wait Register)
This section explains the FRWTR.
This register is effective when ASZ="0b10" (32-bit read mode).
It configures the access method for flash memory except DualFlash area.
bit
7
6
5
4
3
2
1
0
Field
Reserved
RWT
Attribute
RW
RW
Initial Value
1
1
[bit7:2] Reserved bits
The read values are undefined. Ignored on write.
[bit1:0] RWT: Read Wait Cycle
Specifies the access method for flash memory.
Field
bit
Description
RWT
1:0
Read Wait Cycle
00: 0 cycle wait mode (0 latency)
This setting can be used when HCLK is 72 MHz or less.
01: Setting prohibited
10: Flash Accelerator mode 0
This setting can be used when HCLK is 160MHz or less.
This setting must be used when HCLK is over 72 MHz.
11: Flash Accelerator mode 1 (Initial value)
This setting must be used when HCLK is over 160 MHz
In flash accelerator mode, allowing operating Flash Accelerator prefetch buffer function achieves 0 Wait at high speed
operational frequency (up to 200 MHz).
After the Flash Accelerator mode is allowed, allowing operating Flash Accelerator trace buffer function (See Section "
FBFCR (Flash Buffer Control Register)
" achieves additional progress of performance.
When HCLK is 72 MHz or less, 0 cycle wait mode (RWT = “0b00”) is suitable for CPU operation.
In flash accelerator mode, allowing operating the data buffer function. (See Section "
")
Notes:
−
Do not set RWT to "0b00"(0 cycle wait mode) if HCLK exceeds 72 MHz.
While RWT setting is “0b00”, HCLK must not exceed 72 MHz.
−
Do not set RWT to "0b10"(flash accelerator mode 0) if HCLK exceeds 160 MHz.
While RWT setting is “0b10”, HCLK must not exceed 160 MHz.
−
Perform a dummy read to register, after changing this register.
