Document Number: 002-00833 Rev. *L
Page 40 of 74
S29VS256R
S29VS128R
S29XS256R
S29XS128R
8.3
Hardware Data Protection Methods
There are additional hardware methods by which intended or accidental erasure of any sectors can be prevented via hardware
means. The following subsections describes these methods:
8.3.1
V
PP
Method
Once V
PP
input is set to V
IL
, all program and erase functions are disabled and hence all Sectors (including the Secure Silicon
Region) are protected.
8.3.2
Low V
CC
Write Inhibit
When V
CC
is less than V
LKO
, the device does not accept any write cycles. This protects data during V
CC
power-up and power-down.
The command register and all internal program/erase circuits are disabled. Subsequent writes are ignored until V
CC
is greater than
V
LKO
. The system must provide the proper signals to the control inputs to prevent unintentional writes when V
CC
is greater than
V
LKO
.
8.3.3
Write Pulse Glitch Protection
Noise pulses of less than 3 ns (typical) on OE#, WE#, or CE# do not initiate a write cycle.
8.3.4
Power-Up Write Inhibit
If CE# = RESET# = V
IL
and OE# = V
IH
during power up, the device does not accept write commands. The internal state machine is
automatically reset to the idle state on power-up.
8.4
SSR Lock
The SSR Lock consists of two bits. The Customer Secure Silicon Region Protection Bit is bit 0. The Factory Secure Silicon Region
Protection Bit is bit 1. All other bits in this register return “1.” If the Customer Secure Silicon Region Protection Bit is set to “0,” the
Customer Secure Silicon Region is protected and can not be programmed. If this bit is set to “1,” the Customer Secure Silicon
Region is available for programming. Once this area has been programmed, the SSR Lock bit 0 should be programmed to “0.”
8.5
Secure Silicon Region
The Secure Silicon Region provides an extra Flash memory region that may be programmed once and permanently protected from
further programming or erase.
Reads can be performed in the Asynchronous or Synchronous mode.
Sector address supplied during the Secure Silicon Entry command selects the Flash memory array sector that is overlaid by the
Secure Silicon Region address map.
Continuous burst mode reads within Secure Silicon Region wrap from address FFh back to address 00h.
Reads outside of the overlaid sector return memory array data.
The Secure Silicon Region is not accessible when the device is executing an Embedded Algorithm (nor during Program Suspend,
Erase Suspend, or while another AOS is active).
See the Secure Silicon address map for address range of this area.
8.5.1
Factory Secure Silicon Region
The Factory Secure Silicon Region is always protected when shipped from the factory and has the Factory SSR Lock Bit (bit 1)
permanently set to a zero. This prevents cloning of a factory locked part and ensures the security of the ESN and customer code
once the product is shipped to the field.
