Document Number: 002-00833 Rev. *L
Page 18 of 74
S29VS256R
S29VS128R
S29XS256R
S29XS128R
7.1.1
S29VS-R ADM Access
With CE# at V
IL
, WE# at V
IH
, and OE# at V
IH
, the system presents the address to the device and drives AVD# to V
IL
. AVD# is kept
at V
IL
for at least t
AVDP
ns. The address is latched on the rising edge of AVD#.
7.1.2
S29XS-R AADM Access
With CE# at V
IL
, WE# at V
IH
, and OE# at V
IL
, the system presents the upper address bits to DQ and drives AVD# to V
IL
. The upper
address bits are latched when AVD# transitions to V
IH
. The system then drives AVD# to V
IL
again, with OE# at V
IH
and the lower
address bits on the DQ signals. The lower address bits are latched on the next rising edge of AVD#.
7.2
Synchronous (Burst) Read Mode and Configuration Register
The device is capable of continuous sequential burst operation and linear burst operation of a preset length.
In order to use Synchronous (Burst) Read Mode the configuration register bit 15 must be set to 0.
Prior to entering burst mode, the system should determine how many wait states are needed for the initial word of each burst access
(see table below), what mode of burst operation is desired, how the RDY signal transitions with valid data, and output drive strength.
The system would then write the configuration register command sequence. See
Configuration Register on page 23
for further
details.
When the appropriate number of Wait States have occurred, data is output after the
rising edge
of the CLK. Subsequent words are
output t
BACC
after the rising edge of each successive clock cycle, which automatically increments the internal address counter. RDY
indicates the initial latency and any subsequent waits.
7.2.1
S29VS-R ADM Access
To burst read data from the memory array in ADM mode, the system must assert CE# to V
IL
, and provide a valid address while
driving AVD# to V
IL
for one cycle. OE# must remain at V
IH
during the one cycle that AVD# is at V
IL
. The data appears on A/DQ15
-A/DQ0 when CE# remains at V
IL
, after OE# is driven to V
IL
and the synchronous access times are satisfied. The next data in the
burst sequence is read on each clock cycle that OE# and CE# remain at V
IL
.
OE# does not terminate a burst access if it rises to V
IH
during a burst access. The outputs will go to high impedance but the burst
access will continue until terminated by CE# going to V
IH
, or AVD# returns to V
IL
with a new address to initiate a another burst
access.
7.2.2
S29XS-R AADM Access
To burst read data from the memory array in AADM mode, the system must assert CE# to V
IL
, OE# must be driven to V
IL
with AVD#
for one cycle while the upper address is valid. The rising edge of CLK when OE# and AVD# are at V
IL
captures the upper 16 bits of
address. The rising edge of CLK when OE# is at V
IH
and AVD# is at V
IL
latches the lower 16 bits of address. The data appears on
A/DQ15 -A/DQ0 when CE# remains at V
IL
, after OE# is driven to V
IL
and the synchronous access times are satisfied. The next data
in the burst sequence is read on each clock cycle that OE# and CE# remain at V
IL
.
Once OE# returns to V
IH
during a burst read the OE# no longer enables the outputs until after AVD# is at V
IL
with OE# at V
IH
- which
signals that address-low has been captured for the next burst access. This is so that OE# at V
IL
may be used in conjunction with
AVD# at V
IL
to indicate address-high on the A/DQ signals without enabling the A/DQ outputs, thus avoiding data output contention
with Address-high.
The device has a fixed internal address boundary that occurs every 256 Bytes (128 words). A boundary crossing latency of one or
two additional wait states may be required. The device also reads data in 16 byte (8 word) aligned and length groups. When the
initial address is not aligned at the beginning of a 16 byte boundary, additional wait states may be needed when crossing the first 16
byte boundary. The number of additional wait states depends on the clock frequency and starting address location.
