Cypress S29VS128R Manual Download

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Document Number: 002-00833 Rev. *L

Page 13 of 74

S29VS256R
S29VS128R
S29XS256R
S29XS128R

Note:

All tables have been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges that are not explicitly listed
(such as SA008–SA009) have sector starting and ending addresses that form the same pattern as all other sectors of that size. For example, all 128 KB sectors have the
byte address pattern x000000h–x1FFFFh.

6.3

Address/Data Interface

There are two options for connection to the address and data buses.



Address and Data Multiplexed (ADM) mode. On the S29VS-R devices, the upper address is supplied on separate signal inputs

and the lower 16-bits of address are multiplexed with 16-bit data on the A/DQ15 to A/DQ0 I/Os.



Address-high, Address-low, and Data Multiplexed (AADM) mode. On the S29XS-R devices, the upper and lower address are

multiplexed with 16-bit data on the A/DQ15 to A/D0 signal I/Os.

The two options allow use with the traditional address/data multiplexed NOR interface (S29NS family), or an address
multiplexed/data multiplexed interface with the lowest signal count.

6.3.1

ADM Interface (S29VS256R and S29VS128R)

A number of processors use ADM interface as a way to reduce pin count. The system permanently connects the upper address bits
(A[MAX:16] to the device. When AVD# is LOW it connects A[15:0] to DQ[15:0]. The address is latched on the rising edge of AVD#.
When AVD# is HIGH, the system connects the data bus to DQ[15:0]. This results in 16-pin savings from the traditional Address and
Data in Parallel (ADP) interface.

6.3.2

AADM Interface (S29XS256R and S29XS128R)

Signal input and output (I/O) connections on a high complexity component such as an Application Specific Integrated Circuit (ASIC)
are a limited resource. Reducing signal count on any interface of the ASIC allows for either more features or lower package cost.
The memory interface described in this section is intended to reduce the I/O signal count associated with the Flash memory interface
with an ASIC.

The interface is called Address-High, Address-Low, and Data Multiplexed (AADM) because all address and data information is time
multiplexed on a single 16-bit wide bus. This interface is electrically compatible with existing ADM 16-bit wide random access static
memory interfaces but uses fewer address signals. In that sense AADM is a signal count subset of existing static memory interfaces.
This interface can be implemented in existing memory controller designs, as an additional mode, with minimal changes. No new
I/O technology is needed and existing memory interfaces can continue to be supported while the electronics industry adopts this
new interface. ASIC designers can reuse the existing memory address signals above A15 for other functions when an AADM
memory is in use.

Table 6. S29VS/XS128R Sector and Memory Address Map (Bottom Boot)

Bank

Size

(Mbit)

Sector

Count

Sector Size

(Kbyte)

Bank

Sector

Range

Address