Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

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PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C 265
EPx_CR0
1,54h
21.4.7 EPx_CR0
Endpoint Control Registers 0
These registers endpoint control registers.
In the table above, note that the reserved bit is a grayed table cell and is not described in the bit description section below.
Reserved bits must always be written with a value of ‘0’. For additional information, refer to the
Register Definitions on
page 171 in the Full-Speed USB chapter.
7 Stall When this bit is set, the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls
an IN packet if the Mode bits are set to ACK-IN. This bit must be clear for all other modes.
5 NAK_INT_EN When set, this bit causes an endpoint interrupt to be generated even when a transfer completes with
a NAK.
4 ACKed Tx The ACK'ed transaction bit is set whenever the SIE engages in a transaction to the register's end-
point that completes with an ACK packet.
3:0 Mode[3:0] The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of
that endpoint as a result of host packets to the endpoint.
Individual Register Names and Addresses:
1,54h
EP1_CR0 : 1,54h EP2_CR0 : 1,55h EP3_CR0 : 1,56h EP4_CR0 : 1,57h
EP5_CR0 : 1,58h EP6_CR0 : 1,59h EP7_CR0 : 1,5Ah EP7_CR0 : 1,5Bh
7 6 5 4 3 2 1 0
Access : POR RW : 0 RW : 0 RC : 0 RW : 0
Bit Name Stall NAK_INT_EN ACK’ed Tx Mode[3:0]
Bit Name Description
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