Cypress PSoC CY8CTMG20 Series Technical Reference Manual Download

Page: 263 / 308

PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C

263

PMAx_WA

1,34h

21.4.5

PMAx_WA

PSoC Memory Arbiter Write Address Registers

These registers are PSoC Memory Arbiter write address registers.

For additional information, refer to the

in the Full-Speed USB chapter.

7:0

Write Address[7:0]

The value returned when this register is read depends on whether the PMA channel is being used by
the USB SIE or by the M8C.

Individual Register Names and Addresses:

1,34h

PMA0_WA : 1,34h

PMA1_WA : 1,35h

PMA2_WA : 1,36h

PMA3_WA : 1,37h

PMA4_WA : 1,38h

PMA5_WA : 1,39h

PMA6_WA : 1,3Ah

PMA7_WA : 1,3Bh

PMA8_WA : 1,44H

PMA9_WA : 1,45H

PMA10_WA : 1,46H

PMA11_WA : 1,47H

PMA12_W
A

: 1, 48H

PMA13_WA : 1,49h

PMA14_WA : 1,4Ah

PMA15_WA : 1,4Bh

Access : POR

RW : 00

Bit Name

Write Address[7:0]

Bit

Name

Description

[+] Feedback

Summary of Contents for PSoC CY8CTMG20 Series

Page 1: ...TRM PSoC CY8CTMG20x CY8CTMG20xA CY8CTST200 CY8CTST200A Technical Reference Manual TRM Document No 001 53603 Rev C December 11 2009 Cypress Semiconductor 198 Champion Court San Jose CA 95134 1709 Phone...

Page 2: ...s for the sole purpose of creating custom soft ware and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as speci fied in the applicable agre...

Page 3: ...ed Oscillator ILO 67 9 External Crystal Oscillator ECO 69 10 Sleep and Watchdog 73 Section C TrueTouch System 83 11 TrueTouch Module 85 12 I O Analog Multiplexer 99 13 Comparators 101 Section D System...

Page 4: ...4 Contents Overview Feedback...

Page 5: ...n B PSoC Core 23 2 CPU Core M8C 27 2 1 Overview 27 2 2 Internal Registers 27 2 3 Address Spaces 27 2 4 Instruction Set Summary 28 2 5 Instruction Formats 30 2 5 1 One Byte Instructions 30 2 5 2 Two By...

Page 6: ...Posted versus Pending Interrupts 46 5 2 Application Overview 46 5 3 Register Definitions 48 5 3 1 INT_CLR0 Register 48 5 3 2 INT_CLR1 Register 49 5 3 3 INT_CLR2 Register 50 5 3 4 INT_MSK0 Register 51...

Page 7: ...er 71 9 3 3 ECO_CFG Register 71 9 3 4 Related Registers 72 10 Sleep and Watchdog 73 10 1 Architectural Description 73 10 1 1 Sleep Control Implementation Logic 74 10 1 1 1 Wakeup Logic 74 10 1 2 Sleep...

Page 8: ...ors 101 13 1 Architectural Description 101 13 2 Register Definitions 103 13 2 1 CMP_RDC Register 103 13 2 2 CMP_MUX Register 103 13 2 3 CMP_CR0 Register 104 13 2 4 CMP_CR1 Register 104 13 2 5 CMP_LUT...

Page 9: ...1 GPIO Behavior on Power Up 135 16 2 2 Powerup External Reset Behavior 136 16 2 3 GPIO Behavior on External Reset 136 16 3 Register Definitions 137 16 3 1 CPU_SCR1 Register 137 16 3 2 CPU_SCR0 Registe...

Page 10: ...ster 164 19 2 5 PTx_DATA1 Register 164 20 Full Speed USB 165 20 1 Architectural Description 165 20 2 Application Description 165 20 2 1 USB SIE 165 20 2 2 USB SRAM 166 20 2 2 1 PSoC Memory Arbiter 166...

Page 11: ...0_DRx 200 21 3 14 EPx_CNT0 201 21 3 15 EPx_CNT1 202 21 3 16 PMAx_DR 203 21 3 17 AMUX_CFG 204 21 3 18 CMP_RDC 205 21 3 19 CMP_MUX 206 21 3 20 CMP_CR0 207 21 3 21 CMP_CR1 208 21 3 22 CMP_LUT 210 21 3 23...

Page 12: ..._SCR0 258 21 4 Bank 1 Registers 259 21 4 1 PRTxDM0 259 21 4 2 PRTxDM1 260 21 4 3 SPI_CFG 261 21 4 4 USB_CR1 262 21 4 5 PMAx_WA 263 21 4 6 PMAx_RA 264 21 4 7 EPx_CR0 265 21 4 8 TMP_DRx 266 21 4 9 USB_M...

Page 13: ...ing diagrams The sections are as follows Overview Presents the top level architecture helpful information to get started and document history and conventions The PSoC device pinouts are detailed in th...

Page 14: ...U core are the SROM and Flash memory components that provide flexible programming PSoC GPIOs provide connection to the CPU and the True Touch resources of the device Each pin s drive mode is selectabl...

Page 15: ...ock Sources Internal Low Speed Oscillator ILO 6 12 24 MHz Internal Main Oscillator IMO CORE CPU Core M8C Supervisory ROM SROM 8K 16K 32K Flash Nonvolatile Memory SYSTEM RESOURCES SYSTEM BUS SYSTEM BUS...

Page 16: ...s and version enhancements for PSoC Designer free of charge You can order the upgrades from your distributor on CD ROM or download them directly from http www cypress com under Software Also pro vided...

Page 17: ...ample 01010100b or 01000011b Numbers not indicated by an h or b are decimal Units of Measure This table lists the units of measure used in this manual Register Conventions Convention Example Descripti...

Page 18: ...amming IVR interrupt vector read LFSR linear feedback shift register LRb last received bit LRB last received byte LSb least significant bit LSB least significant byte LUT look up table MISO master in...

Page 19: ...Part Pinout Table 1 1 16 Pin QFN COL Part Pinout Pin No Type Name Description CY8CTMG200 16LGXI CY8CTMG200A 16LGXI CY8CTST200 16LGXI CY8CTST200A 16LGXI PSoC Devices Digital Analog 1 IO I P2 5 XTAL Ou...

Page 20: ...K 13 IOHR I P1 6 14 Input XRES Active high external reset with internal pull down 15 IO I P2 0 16 IOH I P0 0 17 IOH I P0 2 18 IOH I P0 4 19 IOH I P0 6 20 Power Vdd Power pin 21 IOH I P0 7 22 IOH I P0...

Page 21: ...1 4 EXTCLK 16 IOHR I P1 6 17 Input XRES Active high external reset with internal pull down 18 IO I P3 0 19 IO I P3 2 20 IO I P2 0 21 IO I P2 2 22 IO I P2 4 23 IO I P2 6 24 IOH I P0 0 25 IOH I P0 2 26...

Page 22: ...pull down 27 IO I P3 0 28 IO I P3 2 29 IO I P3 4 30 IO I P3 6 Pin No Digital Analog Name Description 31 IO I P4 0 32 IO I P4 2 33 IO I P2 0 41 Power Vdd Power pin 34 IO I P2 2 42 NC No connection 35...

Page 23: ...M on page 33 RAM Paging on page 39 Interrupt Controller on page 45 General Purpose I O GPIO on page 55 Internal Main Oscillator IMO on page 63 Internal Low Speed Oscillator ILO on page 67 External Cry...

Page 24: ...rueTouch Analog V Monitor RW 00 0 DBh INT_CLR1 Endpoint3 Endpoint2 Endpoint1 Endpoint0 USB SOF USB Bus Rst Timer2 Timer1 RW 00 0 DCh INT_CLR2 USB_WAKE Endpoint8 Endpoint7 Endpoint6 Endpoint5 Endpoint4...

Page 25: ...2 0 RW 07 1 D3h ECO_TRIM ECO_XGM 2 0 ECO_PL 1 0 RW 00 1 E1h ECO_CFG ECO_LPM ECO_EXW ECO_EX RW 00 SLEEP AND WATCHDOG REGISTERS page 77 0 E3h RES_WDT WDSL_Clear 7 0 W 00 1 EBh SLP_CFG PSSDC 1 0 RW 0 1...

Page 26: ...26 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Section B PSoC Core Feedback...

Page 27: ...in the stack is at address FFh the stack pointer wraps to RAM address 00h It is the firmware developer s responsibility to ensure that the stack does not overlap with user defined variables in RAM Wi...

Page 28: ...C Z 11 4 2 SUB A expr C Z 3E 10 2 MVI A expr Z 6B 7 2 RLC expr C Z 12 6 2 SUB A expr C Z 3F 10 2 MVI expr A 6C 8 2 RLC X expr C Z 13 7 2 SUB A X expr C Z 40 4 1 NOP 6D 4 1 RRC A C Z 14 7 2 SUB expr A...

Page 29: ...2 SUB A expr C Z 70 4 2 AND F expr C Z 5A 5 2 MOV expr X 12 6 2 SUB A expr C Z 41 9 3 AND reg expr expr Z 5B 4 1 MOV A X Z 13 7 2 SUB A X expr C Z 42 10 3 AND reg X expr expr Z 5C 4 1 MOV X A 14 7 2...

Page 30: ...gory for one byte instructions are those that update the internal M8C registers This category holds the largest number of instructions ASL ASR CPL DEC INC MOV POP RET RETI RLC ROMX RRC SWAP These inst...

Page 31: ...ng room for a 16 bit destination address The second three byte instruction format shown in the sec ond row of Table 2 5 is used by the following two address ing modes Destination Direct Source Immedia...

Page 32: ...is set or cleared in response to the result of several instructions It is also manipulated by the flag logic opcodes for example OR F 4 See the PSoC Designer Assembly Language User Guide for more deta...

Page 33: ...he MVW_PP pointers are not disabled by clearing the CPU_F PgMode bits Therefore the POINTER parameter is interpreted as an address in the page indicated by the MVI page pointers when the supervi sory...

Page 34: ...reset to 00h or when user code exe cutes the SSC instruction with an accumulator value of 00h If the checksum of the calibration data is valid the SWBootReset function ends by setting the internal M8...

Page 35: ...to indicate which SRAM pages receive the data 3 1 2 3 WriteBlock Function The WriteBlock function stores data in the Flash No verifi cation of the data is performed but execution time is about 1 ms l...

Page 36: ...spe cific data stored in the Flash during manufacturing The Flash for these tables is separate from the program Flash and is not directly accessible It also returns a revision ID for the die do not co...

Page 37: ...tion are used to move data between SRAM and Flash There fore the MVI write pointer MVW_PP and the MVI read pointer MVR_PP must be specified to the same SRAM page to control the page of RAM used for th...

Page 38: ...l registers to go back to their POR state Then the SROM SWBootReset function executes followed by Flash code execution beginning at address 0x0000 The HWBootReset function only requires that the CPU_A...

Page 39: ...memory paging logic reset state The memory paging architecture consists of five areas Stack Operations Interrupts MVI Instructions Current Page Pointer Indexed Memory Page Pointer The first three of...

Page 40: ...0 If the ISR must change to another SRAM page do this by changing the values of the CPU_F 7 6 bits to enable the special SRAM addressing modes However any change made to the CUR_PP IDX_PP or STK_PP r...

Page 41: ...ly enabled when an interrupt occurs in a PSoC device and is considered the default ISR mode This is because before the ISR is entered the M8C pushes the current value of the CPU_F register onto the st...

Page 42: ...to the Summary Table of the Core Registers on page 24 For additional information refer to the TMP_DRx register on page 266 4 2 2 CUR_PP Register The Current Page Pointer Register CUR_PP sets the effe...

Page 43: ...d address modes to operate on an SRAM page that is not equal to the current SRAM page However the effect this register has on indexed addressing modes is only enabled when the CPU_F 7 6 is set to 10b...

Page 44: ...instruction is executed in a device with more than one page of SRAM the SRAM address that is written by the instruction is determined by the value of the least significant bits in this register Howev...

Page 45: ...on occurs for example a timer expires b a previously posted interrupt is enabled through an update of an interrupt mask register or c an interrupt is pending and GIE is set from 0 to 1 in the CPU Flag...

Page 46: ...red by writing to the appropriate INT_CLRx register A posted interrupt is not pending unless it is enabled by set ting its interrupt mask bit in the appropriate INT_MSKx reg ister All pending interrup...

Page 47: ...es that are available in the PSoC devices Table 5 1 Device Interrupts Interrupt Priority Interrupt Address Interrupt Name 0 Highest 0000h Reset 1 0004h Supply voltage monitor 2 0008h Analog 3 000Ch Tr...

Page 48: ...CLR0 register is interpreted When ENSWINT is cleared the default state writing 1 s to the INT_CLR0 register has no effect However writing 0 s to the INT_CLR0 register when ENSWINT is cleared causes th...

Page 49: ...Endpoint1 Bit 4 Endpoint0 Read 0 no posted interrupt for USB Endpoint0 Read 1 posted interrupt present for USB Endpoint0 Write 0 AND ENSWINT 0 Clear posted interrupt if it exists Write 1 AND ENSWINT 0...

Page 50: ...int8 Bit 3 Endpoint7 Read 0 no posted interrupt for USB Endpoint7 Read 1 posted interrupt present for USB Endpoint7 Write 0 AND ENSWINT 0 Clear posted interrupt if it exists Write 1 AND ENSWINT 0 No e...

Page 51: ...interrupts to be enabled or masked Bit 2 TrueTouch This bit allows TrueTouch interrupts to be enabled or masked Bit 1 Analog This bit allows analog interrupts to be enabled or masked Bit 0 V Monitor T...

Page 52: ..._VC returns the next pending interrupt and clears all pending interrupts when written Bits 7 to 0 Pending Interrupt 7 0 When the register is read the least significant byte LSB of the highest priority...

Page 53: ...Rev C 53 Interrupt Controller with any value all pending and posted interrupts are cleared by asserting the clear line for each interrupt For additional information refer to the INT_VC register on pag...

Page 54: ...54 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Interrupt Controller Feedback...

Page 55: ...ctural Description The GPIO in the CY8CTMG20x CY8CTST200 devices are all uniform except that Port 0 and Port 1 GPIO have stronger high drive In addition to higher drive strength Port 1 GPIO have an op...

Page 56: ...s the PSoC to drive all pins high through a resistor This does not affect any bits that are strongly driven low by the system the PSoC is in However in the second line of code it can not guarantee tha...

Page 57: ...s set and the GPIO pin transitions if not already transitioned appropriately high or low to match the interrupt mode configuration After this happens the INTO line pulls low to assert the GPIO inter r...

Page 58: ...selected by the Alt Select input These data bypass options are selected in one of two ways For internal functions such as I2C and SPI the hardwire automatically selects the bypass mode for the requir...

Page 59: ...register returns the actual pin state as seen by the input buffer This may not be the same as the expected output state if the load pulls the pin more strongly than the pin s configured output drive...

Page 60: ...0b drive mode is used the pin is always read as a zero by the CPU and the pin cannot generate a useful interrupt It is not strictly required that you select High Z mode for analog operation When digit...

Page 61: ...rrupts are controlled at each pin by the PRTxIE registers and also by the global GPIO bit in the INT_MSK0 register For additional information refer to the IO_CFG1 register on page 272 6 2 5 IO_CFG2 Re...

Page 62: ...62 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C General Purpose I O GPIO Feedback...

Page 63: ...uency doubler circuit which produces SYSCLKX2 can be disabled to save power When using an external clock and SYSCLKX2 is needed you cannot dis able the IMO Registers for controlling these operations a...

Page 64: ...eAll Parameters 05h on page 36 has information on the location of various trim set tings stored in Flash tables Firmware needs to read the right trim value for desired frequency and update the IMO_TR...

Page 65: ...ates that the maximum amount of SRAM must be initialized upon watchdog reset to a value of 00h When the bit is 1 the minimum amount of SRAM is initial ized after a watchdog reset For additional inform...

Page 66: ...66 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Internal Main Oscillator IMO 7 3 5 Related Registers OSC_CR2 Register on page 115 CPU_SCR1 Register on page 137 Feedback...

Page 67: ...illator with a nominal frequency of 32 kHz or 1 kHz It is used to generate sleep wakeup interrupts and watchdog resets This oscillator is also used as a clocking source for the digital blocks This blo...

Page 68: ...lects power down mode Set ting this bit high disables the oscillator and current bias when the ILO is powered down which results in slower star tup time Setting this bit low keeps the small current bi...

Page 69: ...O there must be a hold off period before using it as the 32 768 kHz source This hold off period is partially implemented in hardware using the sleep timer Firmware must set up a sleep period of one se...

Page 70: ...scilla tor 5 The ECO becomes the selected source at the end of the one second interval on the edge created by the sleep interrupt logic The one second interval gives the oscilla tor time to stabilize...

Page 71: ...reduction For additional information refer to the ECO_TRIM register on page 270 9 3 3 ECO_CFG Register The ECO Configuration Register provides status and control for the ECO Bit 2 ECO_LPM This bit ena...

Page 72: ...x and CY8CTST200 TRM Document No 001 53603 Rev C External Crystal Oscillator ECO 9 3 4 Related Registers OSC_CR0 Register on page 113 PRTxDR Registers register on page 59 PRTxIE Registers register on...

Page 73: ...0 1 Architectural Description Device components that are involved in Sleep and Watchdog operation are the selected 32 kHz clock the wakeup timer the Sleep bit in the CPU_SCR0 register the sleep circui...

Page 74: ...bus status in the I2C_XSTAT register before putting the device to sleep if there is any I2C data transfer Deep Sleep Mode Configure the I2C_ON bit in the SLP_CFG2 register to 0 then USB Enable bit in...

Page 75: ...The timing of T0 T4 is based on the IMO frequency and the settings in the SLP_CFG3 register For additional information refer to the SLP_CFG3 Register on page 78 3 The maximum worst case duration of th...

Page 76: ...he SLEEP bit in the CPU_SCR0 register Instead the interrupt is taken and the effect of the sleep instruction ignored Note 2 There is no need to enable the Global Interrupt Enable CPU_F register to wak...

Page 77: ...og Reset WDR occurs anywhere from two to three times the current sleep interval setting If the sleep timer is near the beginning of its count the watchdog time out is closer to three times However if...

Page 78: ...the SLP_CFG2 register on page 284 10 3 4 SLP_CFG3 Register The Sleep Configuration Register SLP_CFG3 holds the configuration of the wakeup sequence taps It is strongly recommended to not alter this re...

Page 79: ...y sleep mode the supply voltage monitor circuit is active only during the buzz interval To properly detect and recover from a VDD brown out condi tion the configurable buzz rate must be frequent enoug...

Page 80: ...ere is no difference in wakeup from deep sleep or buzzed sleep because in all cases in order to achieve the power specification the regulator references and core blocks must be shut off 10 4 3 Bandgap...

Page 81: ...isters the WDT terminal count is not reset by the WDR signal when it is asserted but is reset by all other resets This timing is shown in Figure 10 5 Figure 10 5 Watchdog Reset After enabled periodica...

Page 82: ...82 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Sleep and Watchdog Feedback...

Page 83: ...tion encompasses the following chapters TrueTouch Module on page 85 I O Analog Multiplexer on page 99 Comparators on page 101 Top Level TrueTouch Architecture The figure below displays the top level a...

Page 84: ...ata 7 0 RO 00 0 A5h CS_CNTH Data 7 0 RO 00 0 A6h CS_STAT INS COLS COHS PPS INM COLM COHM PPM 00 0 A7h CS_TIMER Timer Count Value 6 0 RW 00 0 A8h CS_SLEW FastSlew 6 0 FS_EN RW 00 0 A9h PRS_CR CS_CLK_OU...

Page 85: ...In the positive charge integration method charge on a sense capacitor is integrated onto a larger capacitor starting from ground The number of cycles required to reach a tar get voltage gives a measu...

Page 86: ...fference is measured by defining an interval of internal oscillator clocks and counting the number of RO periods that occur during this interval See Figure 11 4 Two 8 bit counters are used one clocked...

Page 87: ...h a low pass filter leading into the comparator In addition the IDAC current is set to the desired value as explained later in this section Figure 11 6 Successive Approximation Block Diagram The refer...

Page 88: ...al IDAC setting gives a measurement of capacitance The delay between starting the pin switching and reading the comparator can be set by a firmware delay or by using the 6 bit counter in the TrueTouch...

Page 89: ...forth across the comparator threshold the comparator high out puts are counted in an interval to give a measure of the sense capacitor The larger the sense capacitor the more time the comparator is lo...

Page 90: ...ithms The hardware con sists of two 8 bit up counters with capture that can be optionally chained into a single 16 bit capture counter and an additional 6 bit counter In the charge integration algorit...

Page 91: ...e when it reaches the terminal count The low time of the terminal count pulse is equal to the loaded decimal count value multiplied by the clock period TCpw COUNT VALUEdecimal CLKperiod The period of...

Page 92: ...IMO P and the CPU clock are both derived from the IMO clock but the phase relationship between them is nondeterministic Bits 2 and 1 MODE 1 0 These bits specify the operating mode of the counter logi...

Page 93: ...enables the negative charge inte gration capacitor sense approach This causes the selected sense pin to alternately connect to the analog global bus and ground at the rate selected by the CLKSEL bits...

Page 94: ...nal information refer to the CS_CR3 register on page 214 11 2 5 CS_CNTL Register The TrueTouch Counter Low Byte Register CS_CNTL con tains the current count for the low byte counter Bits 7 to 0 Data 7...

Page 95: ...g a 1 has no effect Mask Bits 3 to 0 Never modify the interrupt mask bits while the block is enabled If modification to bits 3 to 0 is necessary while the block is enabled make certain that the status...

Page 96: ...A 1 routes inverted TrueTouch clock to pin see bit 7 A 0 routes non inverted TrueTouch clock to pin see bit 7 Bit 5 PRS_12BIT This bit allows selection between 8 bit PRS or 12 bit PRS output With 0 th...

Page 97: ...C mode is enabled For additional information refer to the IDAC_D register on page 256 11 3 Timing Diagrams Figure 11 15 Event Timing Mode 00 Figure 11 16 Pulse Width Frequency Timing Mode 01 10 Figure...

Page 98: ...iming RLO Clock Selected Figure 11 19 6 Bit RLO Timer Operation SYSCLK Low Byte Count Enable High Byte Count Enable High Byte Count Low Byte Count 00 01 Low Byte Clock 02 03 04 High Byte Clock 01 02 0...

Page 99: ...o the bus The ana log global bus can be connected as a comparator input Figure 12 1 shows a block diagram of the I O analog mux system Figure 12 1 I O Analog Mux System For each pin the mux capability...

Page 100: ...ith a value of 0 12 2 1 MUX_CRx Registers The Analog Mux Port Bit Enable Registers MUX_CR0 MUX_CR1 MUX_CR2 MUX_CR3 and MUX_CR4 control the connection between the analog mux bus and the corre sponding...

Page 101: ...the comparator system Figure 13 1 Comparators Block Diagram LUT CMP1 To Cap Sense Logic CMP0 LUT Reg Write AMuxBus Reserved P0 1 P0 3 VREF RefLo RefHi Reserved 2 COMP1 Enable Range CMP_CR0 INN1 1 0 CM...

Page 102: ...ut also feeds the set input upon a reset set RS latch The latch is cleared by writing a 0 to the appropriate bit in the CMP_RDC regis ter or by a rising edge from the other comparator LUT The primary...

Page 103: ...is set and held high whenever the comparator 1 LUT goes high since the last time this register was read Refer to the CRST1 bit in the CMP_CR1 register for information on how the latch is cleared Bit 0...

Page 104: ...rator 0 latch is reset upon a register write or by a rising edge from the comparator 1 LUT output Bit 0 CDS0 This bit selects between the comparator 0 LUT and the latched output for the main comparato...

Page 105: ...09 I2C Slave on page 117 System Resets on page 135 POR and LVD on page 143 SPI on page 145 Programmable Timer on page 161 Full Speed USB on page 165 Top Level System Resources Architecture The figure...

Page 106: ...I2C Current Pointer4 0 R 00 0 CDh CPU_BP CPU Base Pointer4 0 RW 00 0 CEh CPU_CP CPU Current Pointer4 0 R 00 0 CFh I2C_BUF Data Buffer 7 0 RW 00 0 D6h I2C_CFG PSelect Stop IE Clock Rate 1 0 Enable RW...

Page 107: ...a Count 7 0 RW 00 0 47h EPx_CNT1 Data Count 7 0 RW 00 0 49h EPx_CNT1 Data Count 7 0 RW 00 0 4Bh EPx_CNT1 Data Count 7 0 RW 00 0 4Dh EPx_CNT1 Data Count 7 0 RW 00 0 4Fh EPx_CNT1 Data Count 7 0 RW 00 0...

Page 108: ...PMAx_WA Write Address 7 0 RW 00 1 3Ch PMAx_RA Read Address 7 0 RW 00 1 3Dh PMAx_RA Read Address 7 0 RW 00 1 3Eh PMAx_RA Read Address 7 0 RW 00 1 3Fh PMAx_RA Read Address 7 0 RW 00 1 40h PMAx_RA Read A...

Page 109: ...xternal clock EXTCLK Whether the external clock or the internal main oscillator is selected all device functions are clocked from a derivative of SYSCLK or are resynchronized to SYSCLK All external as...

Page 110: ...en a switch is made from the IMO to the external clock turn off the IMO to save power You do this by setting the IMODIS bit immediately after the instruction that sets the EXTCLKEN bit When switching...

Page 111: ...ck with a CPU Clock Divider of Two or Greater Figure 14 3 Switch from IMO to External Clock with the CPU Running with a CPU Clock Divider of One CPUCLK IMO Extenal Clock SYSCLK IOW_ EXTCLK bit IMO is...

Page 112: ...t 1 0 of the USBIO_CR1 register is also affected depending on this register setting When this bit is 0 default regardless of the DP and DM state the DPO and DMO bits of USBIO_CR1 are 11b Bit 1 USB_ON...

Page 113: ...P0 4 will not be passed through during sleep modes Please refer to the OUT_P0 register for more details 0 Select Timer output TIMEROUT 1 Select CLK32 Bit 6 P16EN This bit enables pin P1 6 for signal...

Page 114: ...nal Clock on page 110 for more information on the supported frequencies for externally supplied clocks The CPU frequency is changed with a write to the OSC_CR0 register There are eight frequencies gen...

Page 115: ...of internal clock sources and clock nets Bit 4 CLK48MEN This is the 48 MHz clock enable bit 0 disables the bit and 1 enables the bit This register set ting applies only when the device is not in OCD m...

Page 116: ...ignals including the low speed oscillator are synchronized to this clock source The exter nal clock input operates from the clock supplied at P1 4 or P1 1 based on the TSYNC bit in CPU_SCR1 When using...

Page 117: ...Slave Enhanced module is firmware compatible with the previous generation of I2C slave functionality However this module provides new features that are configurable to implement significant flexibili...

Page 118: ...irection of data transfer The addressed slave is required to acknowledge ACK the bus by pulling the data line low during the ninth bit time If the ACK is received the transfer proceeds and the master...

Page 119: ...mmand For example if the base address pointer I2C_BP is set to 4 a read operation begins to read data at location 4 and continues sequentially until the host completes the read operation So if the bas...

Page 120: ...0 A D D D D D D D D 7 6 5 4 3 2 1 0 A D D D D D D D D 7 6 5 4 3 2 1 0 A P A A A A A A A 6 5 4 3 2 1 0 S A A P A A A A A A A 6 5 4 3 2 1 0 R W S A A R R R R R R R R 7 6 5 4 3 2 1 0 A D D D D D D D D 7...

Page 121: ...Restart was sent with the device address and 4 bytes were read On the CPU side a 2 was written to the CPU base address register CPU_BP register and 6 subsequent bytes were read from or written to the...

Page 122: ...ilable in the I2C_DR register to enable the CPU to do a firmware address compare The functionality of this bit is independent of the data buffering mode For additional information refer to the I2C_XCF...

Page 123: ...e of the RAM data buffer Note When in compatibility mode this register is not in use Bits 4 to 0 I2C Base Pointer 4 0 In the EZI2C protocol the first data byte after the slave address transaction in w...

Page 124: ...2C_BP the value of this register sets the starting address for the data location being written or read When this register is written the cur rent address pointer CPU_CP is also updated with the same v...

Page 125: ...FIRST phase are ignored The I O reads that occur only in EXEC phase are taken as actual I O reads for this register So only the following basic M8C register access instruc tions may be used for access...

Page 126: ...ich is nominally 12 MHz or 6 MHz or 24 MHz for CY8CTMG20x and CY8CTST200 unless the PSoC device is in external clocking mode The sampling rate and the baud rate are determined as follows Sample Rate S...

Page 127: ...ck Operation No Disabled The block is disconnected from the GPIO pins P1 5 and P1 7 The pins may be used as general purpose IO When the slave is enabled the GPIO pins are under control of the I2C hard...

Page 128: ...re This bit may only be cleared if the Byte Complete status bit is set If the Stop Interrupt Enable bit is set an interrupt is also generated upon Stop detection It is never automatically cleared Usin...

Page 129: ...pon the current operating mode 0 ACK The master wants to read another byte The slave loads the next byte into the I2C_DR Register and sets the Transmit bit in the I2C_SCR register to continue the tran...

Page 130: ...FG Register If any of the three divider taps is selected that clock is resynchronized to SYSCLK The resulting clock is routed to all of the synchronous elements in the design Figure 15 6 I2C Input Clo...

Page 131: ...nsmitted byte Figure 15 8 Byte Complete Address LRB Timing Figure 15 9 shows the timing for Stop status This bit is set and the interrupt occurs two clocks after the synchronized and filtered SDA line...

Page 132: ...e I2C block responds to transactions during sleep if and only if a The I2C slave block is enabled i e bit 0 of the I2C_CFG Register is set to 1 b1 b If I2C_ON is set or the USB Enable bit of USB_CR0 i...

Page 133: ..._to_sample_mode are asserted asynchronously b This IRQ goes as input to the sleep controller block The sleep controller block wakes the system by clearing the sleep bit c After IMO is operational the...

Page 134: ...134 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C I2C Slave Feedback...

Page 135: ...an XRES pin Watchdog Reset WDR This optional reset occurs when the watchdog timer expires before being cleared by user firmware Watchdog resets default to off Internal Reset IRES This occurs during th...

Page 136: ...the core has powered up a delay of about 1 ms 16 2 3 GPIO Behavior on External Reset During External Reset XRES 1 both P1 0 and P1 1 drive resistive low 0 After XRES deasserts these pins continue to...

Page 137: ...r concern when this bit is set It is pro vided for systems that may be sensitive to boot time so that they can determine if the normal one pass boot time was exceeded For more information on the SWBoo...

Page 138: ...ES Bit 3 Sleep This bit is used to enter Low Power Sleep mode when set To wake up the system this register bit is cleared asynchronously by any enabled interrupt There are two special features of this...

Page 139: ...r XRES deasserts the IMO is started see Figure 16 4 How the XRES configures register reset status bits is shown in 16 4 4 Reset Details on page 141 16 4 3 Watchdog Timer Reset The user has the option...

Page 140: ...llows POR XRES IMO PD IMO not to scale CPU Reset PPOR with no IPOR Reset while PPOR is high and to the end of the next 32K cycle IMO off 1 cycle IMO on before the CPU reset is released Note that at th...

Page 141: ...The IMO is always on for at least one CLK32K cycle before CPU reset is deasserted Table 16 1 Reset Functionality Item IPOR Part of POR PPOR Part of POR XRES WDR Reset Length While POR 1 While PPOR 1...

Page 142: ...142 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C System Resets Feedback...

Page 143: ...on page 187 17 1 Architectural Description The Power on Reset POR and Low Voltage Detect LVD circuits provide protection against low voltage conditions The POR function senses Vcc and Vcore regulated...

Page 144: ...valid values Do not use 11b because it is reserved See the DC POR and LVD Specifications table in the Elec trical Specifications section of the PSoC device data sheet for voltage tolerances for each...

Page 145: ...c signals in a simple connection Figure 18 2 Basic SPI Configuration A device can be a master or slave A master outputs clock and data to the slave device and inputs slave data A slave device inputs c...

Page 146: ...ent interrupts are generated 18 1 3 SPI Slave Function The SPI Slave SPIS offers SPI operating modes 0 3 By default the MSb of the data byte is shifted out first An addi tional option can be set to re...

Page 147: ...an be bypassed by setting the BYPS bit in the SPI_CFG register 18 2 Register Definitions The following registers are associated with the SPI and are listed in address order The register descriptions h...

Page 148: ...om this register is loaded into the Shift register on the following clock edge and a transmission is initiated If a transmission is currently in progress this register serves as a buffer for TX data T...

Page 149: ...ock For additional information refer to the SPI_CR register on page 192 18 2 3 1 SPI Control Register Definitions Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access 0 2Bh SPI_CR LSb F...

Page 150: ...in Bit 1 Int Sel Interrupt Select This bit selects which condi tion produces an interrupt Bit 0 Slave This bit determines whether the block func tions as a master or slave For additional information r...

Page 151: ...d the next data is output on the trailing edge of the clock When the clock phase is 1 it means that the next data is output on the leading edge of the clock and that data is reg istered as an input on...

Page 152: ...disabled all internal state is held in a reset state When the Enable bit in the SPI_CR register is set the reset is synchronously released and the clock generation is enabled All eight taps from the r...

Page 153: ...lock setup time to the next clock a new byte trans mission is initiated An SPIM block receives a byte at the same time that it sends one The SPI Complete or RX Reg Full can be used to determine when t...

Page 154: ...that captures the eighth bit of receive data This status bit is cleared when the user reads the RX Buffer register DR2 SPI Complete is an optional interrupt and is generated when eight bits of data a...

Page 155: ...d as a latch Overrun status is set one half bit clock before RX Reg Full status See Figure 18 7 and Figure 18 8 for status timing relation ships Figure 18 7 SPI Status Timing for Modes 0 and 1 SCLK Mo...

Page 156: ...larity 0 Mode 2 MOSI MISO SCLK Polarity 1 Mode 3 7 6 5 4 3 2 1 0 SS_ TX REG EMPTY RX REG FULL SPI COMPLETE OVERRUN Overrun occurs one half cycle before the last bit is received Last bit of byte is rec...

Page 157: ...abled the MISO output reverts to its idle 1 state All internal state is reset including CR0 status to its configuration specific reset state except for DR0 DR1 and DR2 which are unaffected Normal Oper...

Page 158: ...ing of these status bits are identical to the SPIM with the exception of TX Reg Empty which is covered in the section on TX data queuing Status Clear On Read Refer to the same subsection in SPIM Timin...

Page 159: ...half clock minimum before the leading edge with a knowledge of system latencies and response times Figure 18 11 Mode 0 and 1 Transfer in Progress Figure 18 12 illustrates TX data loading in modes 2 an...

Page 160: ...160 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C SPI Feedback...

Page 161: ...started the programmable timer loads the value con tained in its data registers and counts down to its terminal count of zero The timers output an active high terminal count pulse for one clock cycle...

Page 162: ...9 2 Continuous Operation Example Figure 19 3 One Shot Operation Example PTDATA1 PTDATA0 Clock Start One Shot 00h 00h 03h 02h 01h 00h 03h 02h 01h 00h 03h 02h 01h Count TC 0003h IRQ TC Period TC Period...

Page 163: ...his bit starts the timer counting from a full count The full count is determined by the value loaded into the data registers This bit is cleared when the timer is run ning in one shot mode upon comple...

Page 164: ...er The Programmable Timer Data Register 0 PT0_DATA0 PT1_DATA0 PT2_DATA0 holds the lower 8 bits of the pro grammable timer s count value Bits 7 to 0 DATA 7 0 This is the lower byte of a 16 bit timer Th...

Page 165: ...Application Description The individual components and issues of the USB system are described in detail in the following sections 20 2 1 USB SIE The USB Serial Interface Engine SIE allows the PSoC devi...

Page 166: ...K NAK IN and OUT token Status OUT Only 0010 Accept STALL Check For control endpoint STALL IN and ACK zero byte OUT STALL IN OUT 0011 Accept STALL STALL For control endpoint STALL IN and OUT token Rese...

Page 167: ...l where the endpoint is inactive 2 Write the channel s PMAx_WA register with the first address in SRAM that must be used by this channel 3 Write data to the channel s PMAx_DR register The PMA logic au...

Page 168: ...s 20 2 3 Oscillator Lock The PSoC device can operate without using any external components such as a crystal and still achieve the clock accuracy required for full speed USB It does this by locking it...

Page 169: ...x endpoint 0 data register EP0_DRx and start of frame registers USB_SOFx These registers are reset after the device comes out of sleep An alternative is to simply disconnect from the USB bus before go...

Page 170: ...CY8CTST200 TRM Document No 001 53603 Rev C Full Speed USB Figure 20 2 Transceiver and Regulator Block Diagram VOLTAGE REGULATOR 5V 3 3V S1 1 5K 5K PS2 Pull Up DP DM TEN TD PDN RD DPO RSE0 DMO RECEIVE...

Page 171: ...194 20 3 2 USB_CR0 Register The USB Control Register 0 USB_CR0 is used to set the PSoC sUSB address and enable the USB system resource All bits in this register are reset to zero when a USB bus reset...

Page 172: ...ive mode DMI and DPI determine state of the D and D pins Bit 6 Drive Mode If the IOMode bit is set this bit config ures the D and D pins for either CMOS drive or open drain drive If IOMode is cleared...

Page 173: ...he CPU cannot write to the EP0_DRx registers This prevents firmware from overwriting an incoming setup transaction before firmware has a chance to read the setup data This bit is cleared by any non lo...

Page 174: ...re 0 to 8 For OUT or setup transactions the count is updated by hardware to the number of data bytes received plus two for the CRC bytes Valid values are 2 to 10 For additional information refer to th...

Page 175: ...the two byte CRC are written to the USB s dedicated SRAM If the number of data bytes received is exactly the same as the 9 bit count then only the data is updated into the USB SRAM and the CRC is disc...

Page 176: ...t update for some end point mode settings 0 is error in data received 1 is no error Bit 0 Count MSB This bit is the one MSb of a 9 bit counter The LSb are the Data Count 7 0 bits of the EPx_CNT1 regis...

Page 177: ...t is set whenever the SIE engages in a transaction to the regis ter s endpoint that completes with an ACK packet This bit is cleared by any writes to the register 0 is no ACK ed trans actions since bi...

Page 178: ...case this register always returns the next SRAM address that is used by the PMA channel if a byte is written to the channel s data register PMAx_DR by the M8C For additional information refer to the...

Page 179: ...ext read from the chan nel s PMAx_DR register When the USB SIE reads the PMAx_DR register it also receives a pre loaded value which triggers the PMA logic to fetch the next value in SRAM to be ready f...

Page 180: ...retains its logical high value until firmware clears it Writing a 0 to this bit clears it writing a 1 pre serves its value 0 is no activity 1 is non idle activity D low was detected since the last tim...

Page 181: ...or refer to the IMO_TR1 register on page 286 in the Register Details chapter Bits 2 to 0 Fine Trim 2 0 These bits provide a fine tuning capability to the IMO trim These three bits are the three LSb of...

Page 182: ...182 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Full Speed USB Feedback...

Page 183: ...o as I O space and is broken into two parts Bank 0 user space and Bank 1 configuration space The XIO bit in the Flag register CPU_F determines which bank the user is currently in When the XIO bit is s...

Page 184: ...C RW 246 1D PMA5_DR 5D RW 203 9D DD 1E PMA6_DR 5E RW 203 9E INT_MSK2 DE RW 248 1F PMA7_DR 5F RW 203 9F INT_MSK1 DF RW 249 20 60 CS_CR0 A0 RW 211 INT_MSK0 E0 RW 250 21 AMUX_CFG 61 RW 204 CS_CR1 A1 RW 2...

Page 185: ...CR0 55 265 95 D5 16 EP3_CR0 56 265 96 D6 17 EP4_CR0 57 265 97 D7 18 EP5_CR0 58 265 98 MUX_CR0 D8 RW 271 19 EP6_CRO 59 265 99 MUX_CR1 D9 RW 271 1A EP7_CR0 5A 265 9A MUX_CR2 DA RW 271 1B EP8_CR0 5B 265...

Page 186: ...186 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Section E Registers Feedback...

Page 187: ...register information 4 Detailed register bit descriptions Use the register tables in addition to the detailed register bit descriptions to determine which bits are reserved Reserved bits are grayed ta...

Page 188: ...accessed in both Bank 0 and Bank 1 21 3 1 PRTxDR Port Data Registers These registers allow for write or read access or the current logical equivalent of pin voltage The upper nibble of the PRT4DR reg...

Page 189: ...Register Definitions on page 59 in the GPIO chapter 7 0 Interrupt Enables 7 0 These bits enable the corresponding port pin interrupt Only four LSB are used since this port has four pins 0 Port pin int...

Page 190: ...This register is the SPI s transmit data register For additional information refer to the Register Definitions on page 147 in the SPI chapter 7 0 Data 7 0 Data for selected function Individual Regist...

Page 191: ...This register is the SPI s receive data register For additional information refer to the Register Definitions on page 147 in the SPI chapter 7 0 Data 7 0 Data for selected function Individual Registe...

Page 192: ...al interrupt 4 TX Reg Empty Reset state and the state when the block is disabled is 1 0 Indicates that a byte is currently buffered in the TX register 1 Indicates that a byte is written to the TX regi...

Page 193: ...Start of Frame register 0 For additional information refer to the Register Definitions on page 171 in the Full Speed USB chapter 7 0 Frame Number 7 0 Contains the lower eight bits of the frame number...

Page 194: ...ls and are not described in the bit description section below Reserved bits must always be written with a value of 0 For additional information refer to the Register Definitions on page 171 in the Ful...

Page 195: ...ter Definitions on page 171 in the Full Speed USB chapter 7 USB Enable This bit enables the PSoC device to respond to USB traffic 0 USB disabled 1 USB enabled 6 0 Device Address These bits specify the...

Page 196: ...o manually transmit on D D pins Normally this bit must be cleared to allow the internal SIE to drive the pins The most common reason for manually transmitting is to force a resume state on the bus 0 M...

Page 197: ...drain drive 5 DPI This bit drives the D pin if IOMode 1 4 DMI This pin drives the D pin if IOMode 1 3 PS2PUEN This bit controls the connection of the two internal 5 k pull up resistors to the D and D...

Page 198: ...indicates a valid IN packet was received 5 OUT Received When set this bit indicates an OUT packet was received 4 ACK ed Transaction When set this bit indicates a valid OUT packet has been received an...

Page 199: ...written with a value of 0 For additional information refer to the Register Definitions on page 171 in the Full Speed USB chapter 7 Data Toggle This bit selects the data packet s toggle state 6 Data Va...

Page 200: ...refer to the Register Definitions on page 171 in the Full Speed USB chapter 7 0 Data Byte 7 0 These registers are shared for both transmit and receive Individual Register Names and Addresses 0 38h EP...

Page 201: ...itional information refer to the Register Definitions on page 171 in the Full Speed USB chapter 7 Data Toggle This bit selects the data packet s toggle state 6 Data Valid This bit is used for OUT tran...

Page 202: ...efinitions on page 171 in the Full Speed USB chapter 7 0 Data Count 7 0 These bits are the eight LSb of a 9 bit counter The MSb is the Count MSb of the EPx_CNT0 register Individual Register Names and...

Page 203: ...7 0 When the M8C writes to this register the PMA registers the byte and then stores the value at the address in SRAM indicated by the PMAx_WA register Individual Register Names and Addresses 0 58h PMA...

Page 204: ...logic block toggles regardless of the EN bit setting in CS_CR0 register When this bit is 0 CS_CLK is gated by EN bit in CS_CR0 register This bit is typically used in Proximity detection mode 3 2 ICAPE...

Page 205: ...is bit reads zero when ever the comparator is disabled 4 CMP0D Read only bit that returns the dynamically changing state of comparator 0 This bit reads zero when ever the comparator is disabled 1 CMP1...

Page 206: ...d 10b P0 1 pin 11b P0 3 pin 5 4 INN1 1 0 Comparator 1 Negative Input Select 00b VREF 1 0V 01b Ref Lo approximately 0 6V 10b Ref Hi approximately 1 2V 11b Reserved 3 2 INP0 1 0 Comparator 0 Positive In...

Page 207: ...escribed in the bit description section below Always write reserved bits with a value of 0 For additional information refer to the Register Definitions on page 103 in the Comparators chapter 4 CMP1EN...

Page 208: ...mparator 0 LUT output 4 CDS1 This bit selects the data output for the comparator 1 channel for routing to the capacitive sense logic and comparator 1 interrupt 0 Select the comparator 1 LUT output 1 S...

Page 209: ...9 CMP_CR1 0 7Bh 21 3 21 CMP_CR1 continued 0 CDS0 This bit selects the data output for the comparator 0 channel for routing to the capacitive sense logic and comparator 0 interrupt 0 Select the compara...

Page 210: ...put Function 0h FALSE 1h A AND B 2h A AND B 3h A 4h A AND B 5h B 6h A XOR B 7h A OR B 8h A NOR B 9h A XNOR B Ah B Bh A OR B Ch A Dh A OR B Eh A NAND B Fh TRUE 3 0 LUT0 3 0 Select 1 of 16 logic functio...

Page 211: ...ck works on IMO P pre scaled IMO clock This is also an enable for TrueTouch counters to toggle Note Once the CSD_MODE bit is enabled the IMO P clock is a free running divider clock that cannot be stop...

Page 212: ...CLKSEL 1 0 TrueTouch clock CSCLK selection 00b IMO 01b IMO 2 10b IMO 4 11b IMO 8 4 RLOCLK Relaxation oscillator clock RLO select 0 High byte counter runs on the selected IMO based frequency 1 High by...

Page 213: ...nual connection 1 IDAC is connected to analog global bus 3 CIN_EN 0 Negative charge integration disabled 1 Negative charge integration enabled Selected sense pin s alternately connect to the ana log g...

Page 214: ...e analog global bus 4 REF_EN This bit enables the reference buffer to drive the analog global bus 0 Reference buffer is disabled powered down 1 Reference buffer is enabled Connection to the analog glo...

Page 215: ...fer to the Register Definitions on page 92 in the TrueTouch Module chapter 7 0 Data 7 0 On a read of this register the current count is returned It may only be read when the counter is stopped Note Th...

Page 216: ...ion refer to the Register Definitions on page 92 in the TrueTouch Module chapter 7 0 Data 7 0 On a read of this register the current count is returned It is only read when the counter is stopped Note...

Page 217: ...by writing a 0 back to this bit 5 COHS Counter Carry Out High Status 0 No event detected 1 A carry out from high byte counter was detected Cleared by writing a 0 back to this bit 4 PPS Pulse Width Pe...

Page 218: ...ets the timer count value For additional information refer to the Register Definitions on page 92 in the TrueTouch Module chapter 6 0 Timer Count Value 6 0 Holds the timer count value Individual Regis...

Page 219: ...low the FastSlew setting has no effect After each edge of the relaxation oscillator the counter is re loaded and the fast slewing interval re occurs followed by the slower edge rate at the end of the...

Page 220: ...s bit allows selection between 8 bit PRS or 12 bit PRS output 0 MSB of 8 bit PRS is sent out 1 MSB of 12 bit PRS is sent out 4 PRS_EN This bit is used to enable or disable the PRS block 0 PRS is disab...

Page 221: ...If the bit is set to 1 b1 the timer runs on the CPU clock otherwise the timer runs on the 32 kHz clock 1 One Shot 0 Continuous count mode Timer reloads the count value from the data registers upon ea...

Page 222: ...for the device For additional information refer to the Register Definitions on page 163 in the Programmable Timer chapter 7 0 DATA 7 0 This is the upper byte of a 16 bit timer The lower byte is in th...

Page 223: ...f the count value For additional information refer to the Register Definitions on page 163 in the Programmable Timer chapter 7 0 DATA 7 0 This is the lower byte of a 16 bit timer The upper byte is in...

Page 224: ...If the bit is set to 1 b1 the timer runs on the CPU clock otherwise the timer runs on the 32 kHz clock 1 One Shot 0 Continuos count mode Timer reloads the count value from the data registers upon eac...

Page 225: ...If the bit is set to 1 b1 the timer runs on the CPU clock otherwise the timer runs on the 32 kHz clock 1 One Shot 0 Continuous count mode Timer reloads the count value from the data registers upon ea...

Page 226: ...it is set to a 1 hardware address compare is enabled When enabled bit 3 in the I2C_SCR register is not set Upon a compare the address is automatically ACK ed and upon a mis match the address is automa...

Page 227: ...ved bits with a value of 0 For additional information refer to the Register Definitions on page 122 in the I2C Slave chapter 1 Dir This bit indicates the direction of the current transfer A 1 indicate...

Page 228: ...above note that the reserved bit is a grayed table cell and not described in the bit description section below Always write reserved bits with a value of 0 For additional information refer to the Reg...

Page 229: ...r If the desired transaction is a master write to the slave subsequent bytes are written to the RAM buffer starting with this address and auto incremented see I2C_CP register In case of a read a Start...

Page 230: ...on page 122 in the I2C Slave chapter 4 0 I2C Current Pointer 4 0 This register is set at the same time and with the same value to which the I2C_BP register is set After each completed data byte of th...

Page 231: ...CPU Firmware routines must set this register Similar to the I2C_BP_WR the value of this register sets the starting address for the data location being written to or read from When this register is wr...

Page 232: ...section below Always write reserved bits with a value of 0 For additional information refer to the Register Definitions on page 122 in the I2C Slave chapter 4 0 CPU Current Pointer 4 0 This register...

Page 233: ...ce to the data buffer Whenever this register is read the data at the location pointed to by CPU current pointer CPU_CP is returned Similarly whenever this register is written the data is transferred t...

Page 234: ...ription section below Reserved bits must always be written with a value of 0 For additional information refer to the Register Definitions on page 42 in the RAM Paging chapter 2 0 Page Bits 2 0 Bits de...

Page 235: ...description section below Reserved bits must always be written with a value of 0 For additional information refer to the Register Definitions on page 42 in the RAM Paging chapter 2 0 Page Bits 2 0 Bit...

Page 236: ...tion section below Reserved bits must always be written with a value of 0 For additional information refer to the Register Definitions on page 42 in the RAM Paging chapter 2 0 Page Bits 2 0 Bits deter...

Page 237: ...and are not described in the bit description section below Reserved bits must always be written with a value of 0 For additional information refer to the Register Definitions on page 42 in the RAM Pa...

Page 238: ...s and are not described in the bit description section below Reserved bits must always be written with a value of 0 For additional information refer to the Register Definitions on page 42 in the RAM P...

Page 239: ...tions on page 122 in the I2C Slave chapter 6 P Select I2C Pin Select 0 P1 5 and P1 7 1 P1 0 and P1 1 Note Read the I2C Slave chapter for a discussion of the side effects of choosing the P1 0 and P1 1...

Page 240: ...eceived byte 3 Address 0 Status bit It must be cleared by firmware with a write of 0 to the bit position 1 The received byte is a slave address 2 Transmit Bit is set by firmware to define the directio...

Page 241: ...This register is read only for received data and write only for transmitted data For additional information refer to the Register Definitions on page 122 in the I2C Slave chapter 7 0 Data 7 0 Read rec...

Page 242: ...ite 1 AND ENSWINT 1 Post an interrupt for I2C 6 Sleep Read 0 No posted interrupt for sleep timer Read 1 Posted interrupt present for sleep timer Write 0 AND ENSWINT 0 Clear posted interrupt if it exis...

Page 243: ...it exists Write 1 AND ENSWINT 0 No effect Write 0 AND ENSWINT 1 No effect Write 1 AND ENSWINT 1 Post an interrupt for TrueTouch 1 Analog Read 0 No posted interrupt for Analog Read 1 Posted interrupt...

Page 244: ...sent for USB Endpoint3 Write 0 AND ENSWINT 0 Clear posted interrupt if it exists Write 1 AND ENSWINT 0 No effect Write 0 AND ENSWINT 1 No effect Write 1 AND ENSWINT 1 Post an interrupt for USB Endpoin...

Page 245: ...t an interrupt for USB Start of Frame SOF 2 USB_BUS_RST Read 0 No posted interrupt for USB Bus Reset Read 1 Posted interrupt present for USB Bus Reset Write 0 AND ENSWINT 0 Clear posted interrupt if i...

Page 246: ...NT is set an interrupt is posted in the interrupt controller For additional information refer to the Register Definitions on page 48 in the Interrupt Controller chapter 5 USB_WAKE Read 0 No posted int...

Page 247: ...sted interrupt if it exists Write 1 AND ENSWINT 0 No effect Write 0 AND ENSWINT 1 No effect Write 1 AND ENSWINT 1 Post an interrupt for USB Endpoint6 1 Endpoint5 Read 0 No posted interrupt for USB End...

Page 248: ...of 0 For additional information refer to the Register Definitions on page 48 in the Interrupt Controller chapter 5 USB Wakeup 0 Mask USB Wakeup interrupt 1 Unmask USB Wakeup interrup 4 Endpoint8 0 Mas...

Page 249: ...nmask USB Endpoint3 interrupt 6 Endpoint2 0 Mask USB Endpoint2 interrupt 1 Unmask USB Endpoint2 interrupt 5 Endpoint1 0 Mask USB Endpoint1 interrupt 1 Unmask USB Endpoint1 interrupt 4 Endpoint0 0 Mask...

Page 250: ...r chapter 7 I2C 0 Mask I2C interrupt 1 Unmask I2C interrupt 6 Sleep 0 Mask Sleep interrupt 1 Unmask Sleep interrupt 5 SPI 0 Mask SPI interrupt 1 Unmask SPI interrupt 4 GPIO 0 Mask GPIO interrupt 1 Unm...

Page 251: ...able cells and are not described in the bit description section below Reserved bits must always be written with a value of 0 For additional information refer to the Register Definitions on page 48 in...

Page 252: ...s when written For additional information refer to the Register Definitions on page 48 in the Interrupt Controller chapter 7 0 Pending Interrupt 7 0 Read Returns vector for highest priority pending in...

Page 253: ...chdog timer and the sleep timer together For additional information refer to the Register Definitions on page 77 in the Sleep and Watchdog chapter 7 0 WDSL_Clear 7 0 Any write clears the watchdog time...

Page 254: ...ess mode instructions are referred to Page 0 Indexed Address mode instructions are referred to the RAM page specified by the stack page pointer STK_PP 10b Direct Address mode instructions are referred...

Page 255: ...x F7h 21 3 63 CPU_F continued 1 Zero Set by the M8C CPU Core to indicate whether there was a zero result in the previous logical arith metic operation 0 Not equal to zero 1 Equal to zero 0 GIE 0 M8C...

Page 256: ...C mode is enabled For example a setting of 80h means that the charging current is 128 current units The current size also depends on the IRANGE setting in the CS_CR2 register This setting supplies the...

Page 257: ...on page 137 in the System Resets chapter 7 IRESS This bit is read only 0 Boot phase only executed once 1 Boot phase occurred multiple times 4 3 SLIMO 1 0 These bits set the frequency range for the IMO...

Page 258: ...for GIES Its use is discouraged as the Flag register is now readable at address x F7h read only 5 WDRS Watchdog Reset Status This bit may not be set by user code however it may be cleared by writing a...

Page 259: ...sters are treated as a group These are referred to as DM1 and DM0 or together as DM 1 0 All drive mode bits are shown in the sub table below 10 refers to the combination in order of bits in a given bi...

Page 260: ...are shown in the sub table below 10 refers to the combination in order of bits in a given bit position however this register only controls the most significant bit MSb of the drive mode The upper nibb...

Page 261: ...pass Synchronization 0 All pin inputs are doubled and synchronized 1 Input synchronization is bypassed 3 SS_ Slave Select in Slave mode 0 Slave selected 1 Slave not selected 2 SS_EN_ Internal Slave Se...

Page 262: ...us This bit is only set by the hardware Writing a 0 clears this bit Writing a 1 preserves its present state 0 No activity 1 Non idle activity D Low was detected since the last time the bit was cleared...

Page 263: ...Write Address 7 0 The value returned when this register is read depends on whether the PMA channel is being used by the USB SIE or by the M8C Individual Register Names and Addresses 1 34h PMA0_WA 1 3...

Page 264: ...register is read depends on whether the PMA channel is being used by the USB SIE or by the M8C In the USB case this register always returns the beginning SRAM address for the PMA channel Individual R...

Page 265: ...Mode bits are set to ACK IN This bit must be clear for all other modes 5 NAK_INT_EN When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK 4 ACKed Tx...

Page 266: ...bits in this register are reserved for PSoC devices with 256 bytes of SRAM For additional information refer to the Register Definitions on page 42 in the RAM Paging chapter 7 0 Data 7 0 General purpos...

Page 267: ...his register setting When this bit is 0 default regardless of the DP and DM state the DPO and DMO bits of USBIO_CR1 are 11b 1 USB_ON This bit is used by the IMO DAC block to either work with better DN...

Page 268: ...Main system clock SYSCLK 1 Select either TrueTouch Output signal CS_OUT is selected by CS_OUT 1 0 bits in CS_CR0 register or TrueTouch clock depending upon bit 7 in PRS_CR register 6 P0P7EN This bit e...

Page 269: ...cription section Reserved bits should always be writ ten with a value of 0 See the Application Overview on page 70 for the proper sequence for enabling the ECO 2 0 ECO_ENBUS 2 0 These bits should be w...

Page 270: ...n with a value of 0 For additional information refer to the Register Definitions on page 100 in the I O Analog Multiplexer chapter 4 2 ECO_XGM 2 0 These bits set the amplifier gain The high power mode...

Page 271: ...egister Definitions on page 100 in the I O Analog Multiplexer chapter 7 0 ENABLE 7 0 Each bit controls the connection between the analog mux bus and the corresponding port pin For example MUX_CR2 3 co...

Page 272: ...are no compatibility issues when Port 1 is communicating at regulated voltage levels 0 Standard threshold of VIH VIL 1 Reduce threshold of VIH VIL 2 SPICLK_ON_P10 When set to 1 the SPI clock is mapped...

Page 273: ...ables pin P1 6 for output of the signal selected by the P16D bit 0 No internal signal output to P1 6 1 Output the signal selected by P16D to P1 6 5 P14D Bit selects the data output to P1 4 when P14EN...

Page 274: ...ued 1 P10D Bit selects the data output to P1 0 when P10EN is high 0 Select Sleep Interrupt SLPINT 1 Select Comparator 0 Output CMP0 0 P10EN Bit enables pin P1 0 for output of the signal selected by th...

Page 275: ..._LEVEL 2 0 These bits select output regulated supply 1 0 REG_CLOCK 1 0 The Regulated I O charge pump can operate with a maximum clock speed of 12 MHZ The REG_CLOCK 1 0 bits select clocking options for...

Page 276: ...eep 5 No Buzz This bit allows the bandgap to stay powered during sleep 0 Buzz bandgap during power down 1 Bandgap is always powered even during sleep 4 3 Sleep 1 0 Sleep interval 00b 1 95 ms 512 Hz 01...

Page 277: ...that indicates that the ECO_EX bit was previously written to When this bit is a 1 this indicates that the ECO_CONFIG register was written to and is now locked When this bit is a 0 the register was no...

Page 278: ...sabled Operate from internal main oscillator 1 Enabled Operate from the clock supplied at P1 4 or P1 1 based upon the TSYNC bit in CPU_SCR1 1 IMODIS Internal Oscillator Disable This bit can be set to...

Page 279: ...r Definitions on page 144 in the POR chapter 5 4 PORLEV 1 0 Sets the POR level according to the DC Electrical Specifications in the PSoC device data sheet 3 LVDTBEN Enables reset of the CPU speed regi...

Page 280: ...le cells and are not described in the bit description section below Reserved bits must always be written with a value of 0 For additional information refer to the Register Definitions on page 144 in t...

Page 281: ...d operation The new value must be written at the lower frequency range That is when moving to a higher frequency range change the IMO_TR value and then change the range SLIMO 1 0 in CPU_SCR1 When movi...

Page 282: ...ved bits with a value of 0 For additional information refer to the Register Definitions on page 68 in the Internal Low Speed Oscillator chapter 6 PD_MODE This bit selects power down mode Setting this...

Page 283: ...must always be written with a value of 0 For additional information refer to the Register Definitions on page 77 in the Sleep and Watchdog chapter 7 6 PSSDC 1 0 Sleep Duty Cycle Controls the ratios in...

Page 284: ...Register Definitions on page 77 in the Sleep and Watchdog chapter 3 2 ALT_Buzz 1 0 These bits control additional selections for POR LVD buzz rates 00 Compatibility mode buzz rate is determined by PSSD...

Page 285: ...e doubled for the wakeup sequence 5 4 T2TAP 1 0 These bits control the duration of the T2 T4 sequence see Figure 10 2 on page 75 by selecting a tap from the WakeupTimer Note The T2 delay is only valid...

Page 286: ...it description section Reserved bits should always be written with a value of 0 For additional information refer to the Register Definitions on page 64 in the Internal Main Oscillator chapter 7 0 Fine...

Page 287: ...register where a unit of information is stored algorithm A procedure for solving a mathematical problem in a finite number of steps that frequently involve repetition of an operation ambient temperat...

Page 288: ...nergy and of scattering out of the path to the detector but not including the reduction due to geometric spreading Attenuation is usually expressed in dB B bandgap reference A stable voltage reference...

Page 289: ...awn above the expression being negated for example A A_ A break before make The elements involved go through a disconnected state entering break before the new con nected state make broadcast net A si...

Page 290: ...ine language configuration In a computer system an arrangement of functional units according to their nature number and chief characteristics Configuration pertains to hardware software firmware and d...

Page 291: ...transmitter CRC generator pseudo random number generator or SPI digital logic A methodology for dealing with expressions containing two state variables that describe the behavior of a circuit or syste...

Page 292: ...s of input signals each of which corresponds with one of the two states The circuit remains in either state until it is made to change to the other state by application of the corresponding signal fre...

Page 293: ...data both running at 5V and pulled high with resistors The bus operates at 100 kbits second in standard mode and 400 kbits second in fast mode ICE The in circuit emulator that allows users to test th...

Page 294: ...or bit in a binary number that represents the least significant value typically the right hand bit The bit versus byte distinction is made by using a lower case b for bit in LSb least significant byt...

Page 295: ...In addition to a CPU a microcontroller typically includes memory timing circuits and I O circuitry The rea son for this is to permit the realization of a controller with a minimal quantity of chips th...

Page 296: ...e Boolean Algebra oscillator A circuit that may be crystal controlled and is used to generate a clock frequency output The electrical signal or signals which are produced by an analog or digital block...

Page 297: ...is one type of hardware reset program counter The instruction pointer also called the program counter is a register in a computer processor that indicates where in memory the CPU is executing instruc...

Page 298: ...og signal into a series of digital values or reversed schematic A diagram drawing or sketch that details the elements of a system such as the elements of an electrical circuit or the elements of a log...

Page 299: ...cronym for supervisory read only memory The SROM holds code that is used to boot the device calibrate circuitry and perform Flash operations The functions of the SROM may be accessed in normal user co...

Page 300: ...mpedance The function does not drive any value in the Z state and in many respects may be considered to be disconnected from the rest of the circuit allowing another output to drive the same net U UAR...

Page 301: ...ev C 301 Glossary W watchdog timer A timer that must be serviced periodically If it is not serviced the CPU resets after a specified period of time waveform The representation of a signal as a plot of...

Page 302: ...302 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Glossary Feedback...

Page 303: ...CINTx bits 208 CIP_EN bit 213 CLKSEL bits 212 Clock Phase bit in SPI_CR 192 Clock Polarity bit 192 Clock Rate bits 239 Clock Sel bit 261 clock external digital 110 switch operation 110 clocks digital...

Page 304: ...bit in CS_CR0 register 211 Enable bit 239 ENABLE bits in MUX_CRx registers 271 in SPI_CR register 192 ENSWINT bit 52 251 EP0_CNT register 174 199 EP0_CR register 173 177 EP0_DRx register 174 200 EPx_C...

Page 305: ...plication overview 46 architecture 45 interrupt table 47 latency and priority 46 posted vs pending interrupts 46 register definitions 48 Interrupt Enables bits 189 interrupt modes in GPIO 57 interrupt...

Page 306: ...tions 42 stack operations 40 ReadBlock function in SROM 35 reference of all registers 187 register conventions 17 187 register definitions comparators 103 CPU core 32 digital clocks 112 general purpos...

Page 307: ...k function 36 ReadBlock function 35 SWBootReset function 34 TableRead function 36 WriteBlock function 35 SWBootReset function in SROM 34 switch operation in digital clocks 110 system resets 135 archit...

Page 308: ...308 Index VM bits 279 W watchdog timer reset 139 WDRS bit 258 WDSL_Clear bits 253 WriteAndVerify function in SROM 37 WriteBlock function in SROM 35 X XIO bit 254 XRES reset 139 Z Zero bit 255 Feedback...

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