PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
115
Digital Clocks
14.2.5
OSC_CR2 Register
The Oscillator Control Register 2 (OSC_CR2) configures
various features of internal clock sources and clock nets.
Bit 4: CLK48MEN.
This is the 48 MHz clock enable bit.
'0' disables the bit and '1' enables the bit. This register set-
ting applies only when the device is
not
in OCD mode.
When in OCD mode, the 48 MHz clock is always active.
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access
1,E2h
CLK48MEN
EXTCLKEN
IMODIS
RW : 00
Summary of Contents for PSoC CY8CTMG20 Series
Page 4: ...4 Contents Overview Feedback...
Page 26: ...26 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Section B PSoC Core Feedback...
Page 82: ...82 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Sleep and Watchdog Feedback...
Page 134: ...134 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C I2C Slave Feedback...
Page 142: ...142 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C System Resets Feedback...
Page 160: ...160 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C SPI Feedback...
Page 182: ...182 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Full Speed USB Feedback...
Page 302: ...302 PSoC CY8CTMG20x and CY8CTST200 TRM Document No 001 53603 Rev C Glossary Feedback...
