Cypress PSoC CY8C23533, Technical Reference Manual

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58 Document # 001-20559 Rev. *D
RAM Paging
4.2 Register Definitions
The following registers are associated with RAM Paging and are listed in address order. The register descriptions have an
associated register table showing the bit structure for that register. The bits in the tables that are grayed out are reserved bits
and are not detailed in the register descriptions that follow. Reserved bits should always be written with a value of ‘0’. For a
complete table of RAM Paging registers, refer to the
“Summary Table of the Core Registers” on page 32 .
4.2.1 TMP_DRx Registers
The Temporary Data Registers (TMP_DR0, TMP_DR1,
TMP_DR2, and TMP_DR3) are used to enhance the perfor-
mance in multiple SRAM page PSoC devices.
These registers have no pre-defined function (for example,
the compiler and hardware do not use these registers) and
exist for the user to use as desired.
Bits 7 to 0: Data[7:0]. Due to the paged SRAM architec-
ture of PSoC devices with more than 256 bytes of SRAM, a
value in SRAM may not always be accessible without first
changing the current page.
The TMP_DRx registers are readable and writable registers
that are provided to improve the performance of multiple
SRAM page PSoC devices, by supplying some register
space for data that is always accessible.
For expanded listing of TMP_DRx registers, refer to “Sum-
mary Table of the Core Registers” on page 32 . For addi-
tional information, refer to TMP_DRx register on page 72 .
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
x,6xh TMP_DR
x Data[7:0] RW : 00
LEGEND
x An ‘x’ before the comma in the address field indicates that this register can be read or written to no matter what bank is used. An “x” after the comma in the
address field indicates that there are multiple instances of the register.