Cypress PSoC CY8C23533, Technical Reference Manual

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56 Document # 001-20559 Rev. *D
RAM Paging
4.1.2 Stack Operations
As mentioned previously, the paging architecture's reset
state puts the PSoC in a mode that is identical to that of a
256 byte PSoC device. Therefore, upon rest, all memory
accesses are to Page 0. The SRAM page that stack opera-
tions uses is determined by the value of the three least sig-
nificant bits of the Stack Page Pointer register (STK_PP).
Stack operations have no dependency on the PgMode bits
in the CPU_F register. Stack operations are those that use
the Stack Pointer (SP) to calculate their affected address.
Refer to the
PSoC Designer Assembly Language User
Guide for more information on all M8C instructions.
Stack memory accesses must be treated as a special case.
If they are not, the stack could be fragmented across several
pages. To prevent the stack from becoming fragmented, all
instructions that operate on the stack automatically use the
page indicated by the STK_PP register. Therefore, if a CALL
is encountered in the program, the PSoC device automati-
cally pushes the program counter onto the stack page indi-
cated by STK_PP. Once the program counter is pushed, the
SRAM paging mode automatically switches back to the pre-
call mode. All other stack operations, such as RET and POP,
follow the same rule as CALL. The stack is confined to a sin-
gle SRAM page and the SP wraps from 00h to FFh and FFh
to 00h. The user code must ensure that the stack is not
damaged due to stack wrapping.
Because the value of the STK_PP register can be changed
at any time, it is theoretically possible to manage the stack in
such a way as to allow it to grow beyond one SRAM page or
manage multiple stacks. However, the only supported use of
the STK_PP register is when its value is set prior to the first
stack operation and not changed again.
4.1.3 Interrupts
Interrupts, in a multi-page SRAM PSoC device, operate the
same as interrupts in a 256 byte PSoC device. However,
because the CPU_F register is automatically set to 0x00 on
an interrupt and because of the non-linear nature of inter-
rupts in a system, other parts of the PSoC memory paging
architecture can be affected.
Interrupts are an abrupt change in program flow. If no spe-
cial action is taken on interrupts by the PSoC device, the
interrupt service routine (ISR) could be thrown into any
SRAM page. To prevent this problem, the special address-
ing modes for all memory accesses, except for stack and
MVI, are disabled when an ISR is entered. The special
addressing modes are disabled when the CUP_F register is
cleared. At the end of the ISR, the previous SRAM address-
ing mode is restored when the CPU_F register value is
restored by the RETI instruction.
Therefore, all interrupt service routine code starts execution
in SRAM Page 0. If it is necessary for the ISR to change to
another SRAM page, it can be accomplished by changing
the values of the CPU_F[7:6] bits to enable the special
SRAM addressing modes. However, any change made to
the CUR_PP, IDX_PP, or STK_PP registers persist after the
ISR returns. Therefore, the ISR should save the current
value of any paging register it modifies and restore its value
before the ISR returns.
4.1.4 MVI Instructions
MVI instructions use data page pointers of their own
(MVR_PP and MVW_PP). This allows a data buffer to be
located away from other program variables, but accessible
without changing the Current Page Pointer register
(CUR_PP).
An MVI instruction performs three memory operations. Both
forms of the MVI instruction access an address in SRAM
that holds the data pointer (a memory read 1st access),
incrementing that value and then storing it back in SRAM (a
memory write 2nd access). This pointer value must reside in
the current page, just as all other non-stack and non-
indexed operations on memory must. However, the third
memory operation uses the MVx_PP register. This third
memory access can be either a read or a write, depending
on which MVI instruction is used. The MVR_PP pointer is
used for the MVI instruction that moves data into the accu-
mulator. The MVW_PP pointer is used for the MVI instruc-
tion that moves data from the accumulator into SRAM. The
MVI pointers are always enabled, regardless of the state of
the Flag register page bits (CPU_F register).
4.1.5 Current Page Pointer
The Current Page Pointer is used to determine which SRAM
page should be used for all memory accesses. Normal
memory accesses are those not covered by other pointers
including all non-stack, non-MVI, and non-indexed memory
access instructions. The normal memory access instructions
have the SRAM page they operate on determined by the
value of the CUR_PP register. By default, the CUR_PP reg-
ister has no affect on the SRAM page used for normal mem-
ory access, because all normal memory access is forced to
SRAM Page 0.
The upper bit of the PgMode bits in the CPU_F register
determines whether or not the CUR_PP register affects nor-
mal memory access. When the upper bit of the PgMode bits
is set to ’0’, all normal memory access is forced to SRAM
Page 0. This mode is automatically enabled when an ISR is
entered. This is because, before the ISR is entered, the
M8C pushes the current value of the CPU_F register onto
the stack and then clears the CPU_F register. Therefore, by
default, any normal memory access in an ISR is guaranteed
to occur in SRAM Page 0.