Cypress PSoC CY8C23533, Technical Reference Manual

Page: 46 / 410

46 Document # 001-20559 Rev. *D
Supervisory ROM (SROM)
1. halt
2. SSCOP: mov [KEY1], 3ah
3. mov X, SP
4. mov A, X
5. add A, 3
6. mov [KEY2], A
3.1.1 Additional SROM Feature
The SROM has the following additional feature.
Return Codes: These aid in the determination of success
or failure of a particular function. The return code is stored in
KEY1’s position in the parameter block. The CheckSum and
TableRead functions do not have return codes because
KEY1’s position in the parameter block is used to return
other data.
Note Read, write, and erase operations may fail if the target
block is read or write protected. Block protection levels are
set during device programming and cannot be modified from
code in the PSoC device.
3.1.2 SROM Function Descriptions
3.1.2.1 SWBootReset Function
The SROM function SWBootReset is responsible for transi-
tioning the device from a reset state to running
user code.
See “System Resets” on page 313 for more information on
what events cause the SWBootReset function to execute.
The SWBootReset function is executed whenever the
SROM is entered with an M8C accumulator value of 00h;
the SRAM parameter block is not used as an input to the
function. This happens, by design, after a
hardware reset,
because the M8C's accumulator is reset to 00h or when
user code executes the SSC instruction with an accumulator
value of 00h.
If the checksum of the calibration data is valid, the
SWBootReset function ends by setting the internal M8C reg-
isters (CPU_SP, CPU_PC, CPU_X, CPU_F, CPU_A) to 00h
writing 00h to most SRAM addresses in SRAM Page 0 and
then begins to execute user code at address 0000h. (See
Table 3-4 and the following paragraphs for more information
on which SRAM addresses are modified.) If the checksum is
not valid, an internal reset is executed and the boot process
starts over. If this condition occurs, the internal reset status
bit (IRESS) is set in the CPU_SCR1 register.
Table 3-4 documents the value of all the SRAM addresses in
Page 0 after a successful SWBootReset. A cell in the table
with “xx” indicates that the SRAM address is not modified by
the SWBootReset function. A hex value in a cell indicates
that the address should always have the indicated value
after a successful SWBootReset. A cell with a “??” in it indi-
cates that the value, after a SWBootReset, is determined by
the value of IRAMDIS bit in the CPU_SCR1 register. If
IRAMDIS is not set, these addresses are initialized to 00h. If
IRAMDIS is set, these addresses are not modified by a
SWBootReset after a watchdog reset.
The IRAMDIS bit allows variables to be preserved even if a
watchdog reset (WDR) occurs. The IRAMDIS bit is reset by
all system resets except watchdog reset. Therefore, this bit
is only useful for watchdog resets and not general resets.
Table 3-2. SROM Function Variables
Variable Name SRAM Address
KEY1 / RETURN CODE 0,F8h
KEY2 0,F9h
BLOCKID 0,FAh
POINTER 0,FBh
CLOCK 0,FCh
Reserved 0,FDh
DELAY 0,FEh
Reserved 0,FFh
Table 3-3. SROM Return Code Descriptions
Return Code Value Description
00h Success
01h Function not allowed due to level of protection on
the block.
02h Software reset without hardware reset.
03h Fatal error, SROM halted.