Cypress PSoC CY8C23533, Technical Reference Manual

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28 Document # 001-20559 Rev. *D
Pin Information
1.1.2 32-Pin Part Pinout
The 32-pin part is for the CY8C23533 PSoC device.
Table 1-3. 32-Pin Part Pinout (QFN)
Pin
No.
Type
Pin
Name
Description
CY8C23533 32-Pin PSoC Device
Digital Analog
1 IO P2[7] GPIO
2 IO P2[5] GPIO
3 IO I P2[3] Direct Switched Capacitor Block Input
4 IO I P2[1] Direct Switched Capacitor Block Input
5 IO AVref P3[0]* GPIO/ADC Vref (optional)
6 NC No Connection
7 IO P1[7] I2C Serial Clock (SCL)
8 IO P1[5] I2C Serial Data (SDA)
9 NC No Connection
10 IO P1[3] GPIO
11 IO P1[1]** GPIO, Crystal Input (XTALin), I2C Serial
Clock (SCL), ISSP-SCLK
12 Power Vss Ground Connection
13 IO P1[0]** GPIO, Crystal Output (XTALout), I2C
Serial Data (SDA), ISSP-SDATA
14 IO P1[2] GPIO
15 IO P1[4] GPIO, External Clock IP
16 NC No Connection
17 IO P1[6] GPIO
18 Input XRES Active High External Reset with Internal
Pull Down
19 IO I P2[0] Direct Switched Capacitor Block Input
20 IO I P2[2] Direct Switched Capacitor Block Input
21 IO P2[4] External Analog Ground (AGnd)
22 IO P2[6] External Voltage Reference (VRef)
23 IO I P0[0] Analog Column Mux Input and ADC Input
24 IO I P0[2] Analog Column Mux Input and ADC Input
25 NC No Connection
26 IO I P0[4] Analog Column Mux Input and ADC Input
27 IO I P0[6] Analog Column Mux Input and ADC Input
28 Power Vdd Supply Voltage
29 IO I P0[7] Analog Column Mux Input and ADC Input
30 IO IO P0[5] Analog Column Mux Input, Column Output
and ADC Input
31 IO IO P0[3] Analog Column Mux Input, Column Output
and ADC Input
32 IO I P0[1] Analog Column Mux Input.and ADC Input
LEGEND : A = Analog, I = Input, and O = Output.
* Even though P3[0] is an odd port, it resides on the left side of the pinout.
** ISSP pin, which is not High Z at POR.
GPIO, P2[7]
GPIO, P2[5]
A , I, P2[3]
A , I, P2[1]
AVref, P3[0]
NC
QFN
(Top View)
9
10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
32 31 30 29 28 27 26 25
P
0
[1
],
A
,
I
P
0
[3
],
A
,
IO
P
0
[5
],
A
,
IO
P
0
[7
],
A
,
I
Vd
d
P
0
[6
],
A
,
I
P
0
[4
],
A
,
I
NC
I2C SCL, P1[7]
I2C SDA, P1[5]
P 0[2 ], A , I
P 0[0 ], A , I
XRES
P 1[6 ], GPIO
NC
GP
IO
P
1
[3
]
I2
C
SC
L,
XT
AL
in,
P1
[1
]
Vs
s
I2
C
SD
A
,
XT
A
L
ou
t,
P1
[0
]
GP
IO
P
1
[2
]
G
P
IO
, E
X
T
C
L
K
,
P
1
[4
]
NC
P 2[6 ], Vref
P 2[4 ], AGnd
P 2[2 ], A , I
P 2[0 ], A , I