Cypress PSoC CY8C23533, Technical Reference Manual

Page: 245 / 410

Document # 001-20559 Rev. *D 181
Digital Blocks
The dead band has two inputs: a PWM reference signal and
a KILL signal. The PWM reference signal may be derived
from one of two sources. By default, it is hardwired to be the
primary output of the previous block. This previous block
output is wired as an input to the 16-to-1 clock input mux. In
the dead band case, as the previous block output is wired
directly to the dead band reference input. If this mode is
used, a PWM, or some other
waveform generator, must be
instantiated in the previous digital block. There is also an
optional Bit Bang mode. In this mode, firmware toggles a
register bit to generate a PWM reference; and therefore, the
dead band may be used as a standalone block.
The KILL signal is derived from the data input signal to the
block. Mode [1:0] is encoded as the Kill Type. In all cases
when kill is asserted, the output is forced low immediately.
Mode bits are encoded for kill options and are detailed in the
following table.
When the block is initially enabled, both outputs are low.
After enabling, a positive or negative edge of the incoming
PWM reference enables the counter. The counter counts
down from the period value to terminal count. At terminal
count, the counter is disabled and the selected phase is
asserted high. On the opposite edge of the PWM input, the
output that was high is negated low and the process is
repeated with the opposite phase. This results in the gener-
ation of a two phase non-overlapping clock matching the fre-
quency and pulse width of the incoming PWM reference, but
separated by a dead time derived from the period and the
input clock.
There is a deterministic relationship between the incoming
PWM reference and the output phases. The positive edge of
the reference causes the primary output to be asserted to '1'
and the negative edge of the reference causes the auxiliary
output to be asserted to '1'.
17.1.8.1 Usability Exceptions
The following are usability exceptions for the dead band
function.
1. The dead band function may not be chained.
2. Programming a dead band period value of 00h is not
supported. The block output is undefined under this con-
dition.
3. If the period (of either the high time or the low time of
the reference input) is less than the programmed dead
time, then the associated output phase is held low.
4. DR0 may only be read (to transfer DR0 data to DR2)
when the block is disabled.
5. If the asynchronous KILL signal is being used in a given
application, the output of the dead band cannot be con-
nected directly to the input of another digital block in the
same row. Since the kill is asynchronous, the digital
block output must be resynchronized through a row input
before using it as a digital block input.
17.1.8.2 Block Interrupt
The dead band block has one fixed interrupt source, which
is the Phase 1 primary output clock. When the KILL signal is
asserted, the interrupt follows the same behavior of the
Phase 1 output with respect to the various KILL modes.
17.1.9 CRCPRS Function
A Cyclic Redundancy Check/Pseudo Random Sequence
(CRCPRS) function consists of a polynomial register, a
Lin-
ear Feedback Shift Register (LFSR) , and a seed register.
(See Figure 17-4 on page 182 .) When the CRCPRS block is
disabled and a seed value is written into DR2, the seed
value is also loaded into DR0. When the CRCPRS is
enabled, and synchronous clock and data are applied to the
inputs, a CRC is computed on the
serial data input stream.
When the data input is forced to '0', then the block functions
as a pseudo random sequencer (PRS) generator with the
output data generated at the clock rate. The most significant
bit (MSb) of the CRCPRS function is the primary output.
The CRCPRS has a selection of compare modes between
DR0 and DR2. The default behavior of the compare is
DR0==DR2. When the PRS function cycles through the
seed value as one of the valid counts, the compare output is
asserted high for one clock cycle. This is regarded as the
epoch of the pseudo random sequence. The mode bits can
be used to set other compare types. Setting Mode bit 0 to '1'
causes the compare behavior to revert to DR0 <= DR2 or
DR0 < DR2, depending upon Mode bit 1. The compare
value is the auxiliary output. An interrupt is generated on
compare true.
CRCPRS mode offers an optional pass function. By setting
the Pass Mode bit in the CR0 register (bit 1), the CRCPRS
function is overridden. In this mode, the data input is passed
transparently to the primary output and an interrupt is gener-
ated on the rising of the data input. Similarly, the CLK input
is passed transparently to the auxiliary output. This can only
be used to pass signals to the global outputs. If the output of
a pass function is needed as an input to another digital
block, it must be resynchronized through the globals and
row inputs.
Table 17-2. Dead Band KILL Options
Mode [1:0] Description
00b Synchronous Restart KILL mode. Internal state is reset and
reference edges are ignored, until the KILL signal is negated.
01b Disable KILL mode. Block is disabled. KILL signal must be
negated and user must re-enable the block in firmware to
resume operation.
10b Asynchronous KILL mode. Outputs are low only for the dura-
tion that the KILL signal is asserted, subject to a minimum
disable time between one-half to one and one-half clock
cycles. Internal state is unaffected.
11b Reserved.