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PSoC 4000 TRM

PSoC 4000 Family

PSoC

4 Architecture Technical Reference

Manual (TRM)

Document No. 001-89309 Rev. *D

May 31, 2017

Cypress Semiconductor

198 Champion Court

San Jose, CA 95134-1709

Phone (USA): +1.800.858.1810

Phone (Intnl): +1.408.943.2600

www.cypress.com

Summary of Contents for PSoC 4

Page 1: ...ily PSoC 4 Architecture Technical Reference Manual TRM Document No 001 89309 Rev D May 31 2017 Cypress Semiconductor 198 Champion Court San Jose CA 95134 1709 Phone USA 1 800 858 1810 Phone Intnl 1 40...

Page 2: ...RCHANTABILITY AND FITNESS FOR A PARTICULAR PUR POSE To the extent permitted by applicable law Cypress reserves the right to make changes to this document without fur ther notice Cypress does not assum...

Page 3: ...ion D System Resources Subsystem SRSS 43 7 I O System 45 8 Clocking System 55 9 Power Supply and Monitoring 61 10 Chip Operational Modes 67 11 Power Modes 69 12 Watchdog Timer 73 13 Reset System 77 14...

Page 4: ...4 PSoC 4000 Family PSoC 4 Architecture TRM Document No 001 89309 Rev D Contents...

Page 5: ...5 1 6 2 Serial Communication BlocksI2C Block 15 1 7 Special Function Peripherals 15 1 7 1 CapSense 15 1 8 Program and Debug 16 2 Getting Started 17 2 1 Support 17 2 2 Product Upgrades 17 2 3 Developme...

Page 6: ...n Priority 35 5 7 Enabling and Disabling Interrupts 36 5 8 Exception States 36 5 8 1 Pending Exceptions 36 5 9 Stack Usage for Exceptions 37 5 10 Interrupts and Low Power Modes 37 5 11 Exceptions Init...

Page 7: ...V to 5 5 V Unregulated Supply 63 9 2 2 Direct 1 71 V to 1 89 V Regulated Supply 63 9 2 3 VDDIO Supply 64 9 3 How It Works 64 9 3 1 Regulator Summary 64 9 4 Voltage Monitoring 65 9 4 1 Power On Reset...

Page 8: ...Internal and External Clock Operation in I2C 89 15 2 8 Wake up from Sleep 91 15 2 9 Master Mode Transfer Examples 92 15 2 10 Slave Mode Transfer Examples 94 15 2 11 EZ Slave Mode Transfer Example 96...

Page 9: ...he PSoC 4 Device 143 18 5 1 SWD Port Acquisition 143 18 5 2 SWD Programming Mode Entry 143 18 5 3 SWD Programming Routines Executions 143 18 6 PSoC 4 SWD Debug Interface 144 18 6 1 Debug Control and C...

Page 10: ...10 PSoC 4000 Family PSoC 4 Architecture TRM Document No 001 89309 Rev D Contents Index 177...

Page 11: ...Getting Started chapter on page 17 Document Construction chapter on page 19 Document Revision History Revision Issue Date Origin of Change Description of Change A April 15 2014 NIDH New PSoC 4000 TRM...

Page 12: ...12 PSoC 4000 Family PSoC 4 Architecture TRM Document No 001 89309 Rev D...

Page 13: ...hese characteristics High performance 32 bit single cycle Cortex M0 CPU core Capacitive touch sensing CapSense Configurable Timer Counter PWM block Configurable I2C block with master slave and multi m...

Page 14: ...er operation with extensive clock gating It uses 16 bit instructions and executes a subset of the Thumb 2 instruc tion set This instruction set enables fully compatible binary upward migration of the...

Page 15: ...in the range 1 71 V to 5 5 V PSoC 4 has two low power modes Sleep and Deep Sleep in addition to the default Active mode In Active mode the CPU runs with all the logic powered In Sleep mode the CPU is...

Page 16: ...12 V reference which can be used for general purposes if CapSense is not used 1 8 Program and Debug PSoC 4 devices support programming and debugging fea tures of the device via the on chip SWD interf...

Page 17: ...on DVD ROM you can also download them directly from www cypress com psoccreator Critical updates to system documentation are also provided in the Documentation section 2 3 Development Kits The Cypres...

Page 18: ...18 PSoC 4000 Family PSoC 4 Architecture TRM Document No 001 89309 Rev D Getting Started...

Page 19: ...ted in bold italic font throughout Registers Technical Reference Manual Supplies all device register details summarized in the technical reference man ual This is an additional document 3 2 Documentat...

Page 20: ...ransfer bus API application programming interface APOR analog power on reset BC broadcast clock BOD brownout detect BOM bill of materials BR bit rate BRA bus request acknowledge BRQ bus request CAN co...

Page 21: ...n ratio PSSDC power system sleep duty cycle PWM pulse width modulator RAM random access memory RETI return from interrupt RF radio frequency ROM read only memory RMS root mean square RW read write SAR...

Page 22: ...22 PSoC 4000 Family PSoC 4 Architecture TRM Document No 001 89309 Rev D Document Construction...

Page 23: ...D 23 Section B CPU System This section encompasses the following chapters Cortex M0 CPU chapter on page 25 Interrupts chapter on page 31 Top Level Architecture CPU System Block Diagram SWD TC Cortex...

Page 24: ...24 PSoC 4000 Family PSoC 4 Architecture TRM Document No 001 89309 Rev D...

Page 25: ...C a SYSTICK timer and debug This section gives an overview of the Cortex M0 processor For more details see the ARM Cortex M0 user guide or technical reference manual both available at www arm com 4 1...

Page 26: ...s space is divided into the regions shown in Table 4 1 Note that code can be executed from the code and SRAM regions Table 4 1 Cortex M0 Address Map Address Range Name Use 0x00000000 0x1FFFFFFF Code P...

Page 27: ...lue from address 0x00000000 LR R14 RW Undefined The link register LR is register R14 It stores the return information for subroutines function calls and exceptions PC R15 RW 0x00000004 The program cou...

Page 28: ...instruction This ensures that instructions after the ISB execute using the new stack pointer In handler mode explicit writes to the CONTROL register are ignored because the MSP is always used The exc...

Page 29: ...tionally BICS Bit clear BKPT Breakpoint BL Branch with link BLX Branch indirect with link BX Branch indirect CMN Compare negative CMP Compare CPSID Change processor state disable interrupts CPSIE Chan...

Page 30: ...30 PSoC 4000 Family PSoC 4 Architecture TRM Document No 001 89309 Rev D Cortex M0 CPU...

Page 31: ...atures Supports 9 interrupts Nested vectored interrupt controller NVIC integrated with CPU core yielding low interrupt latency Vector table may be placed in either flash or SRAM Configurable priority...

Page 32: ...CPU to execute the appropriate exception handler 5 3 2 Level and Pulse Interrupts NVIC supports both level and pulse signals on the interrupt lines IRQ0 to IRQ8 The classification of an interrupt as...

Page 33: ...he handler in flash The reset exception address in the SRAM vector table is never used because VECT_IN_RAM is 0 on reset Also when the SYSREQ bit of the CPUSS_SYSREQ regis ter is set reads of flash ad...

Page 34: ...rdFault exception handler but it does permit the han dler to perform an exception return and continue execution in cases where software has the ability to recover from the fault situation 5 4 4 Superv...

Page 35: ...cuted continuously See the I O System chapter on page 53 for details on GPIO interrupts 5 6 Exception Priority Exception priority is useful for exception arbitration when there are multiple exceptions...

Page 36: ...egister IPSR which is also used to store the active exception number The VECTPENDING bits 20 12 in the CM0_ICSR store the exception number of the highest priority pend ing exception This value is zero...

Page 37: ...er to store the general purpose register contents After the stack push operations the CPU enters handler mode to execute the exception handler When another higher priority exception occurs while execu...

Page 38: ...s on the specific exception required b Define the exception handler function and write the address of the function to the exception vector table Table 5 1 gives the exception vector table format the e...

Page 39: ...Section C Memory System This section presents the following chapter Memory Map chapter on page 41 Top Level Architecture Memory System Block Diagram SPCIF FLASH 16 KB Read Accelerator SRAM 2 kB SROM 4...

Page 40: ...40 PSoC 4000 Family PSoC 4 Architecture TRM Document No 001 89309 Rev D...

Page 41: ...fixed function I2C block For more information see the Cortex M0 CPU chapter on page 25 6 2 How It Works The PSoC 4 memory map is detailed in the following tables For additional information refer to th...

Page 42: ...0000 0x200007FF 2 KB SRAM 0x40100000 0x4011FFFF CPU subsystem registers 0x40020000 0x40023FFF I O port control high speed I O matrix registers 0x40040000 0x40043FFF I O port registers 0x40050000 0x400...

Page 43: ...55 Power Supply and Monitoring chapter on page 61 Chip Operational Modes chapter on page 67 Power Modes chapter on page 69 Watchdog Timer chapter on page 73 Reset System chapter on page 77 Device Secu...

Page 44: ...44 PSoC 4000 Family PSoC 4 Architecture TRM Document No 001 89309 Rev D...

Page 45: ...eatures The PSoC 4 GPIOs have these features Analog and digital input and output capabilities Eight drive strength modes Edge triggered interrupts on rising edge falling edge or on both the edges on p...

Page 46: ...etween a peripheral selected by the user and the pin The CapSense block is connected to the GPIO pins through the AMUX buses 7 3 I O Cell Architecture Figure 7 2 shows the I O cell architecture It com...

Page 47: ...IO_PRTx_PC 3y 2 3y In OE PIN VDD VDDIO VDD VDDIO Digital Output Path GPIO_PRTx_DR y ACTIVE_0 TCPWM ACTIVE_1 TCPWM ACTIVE_2 TCPWM ACTIVE_3 CSD Comparator DEEP_SLEEP_1 SWD DEEP_SLEEP_0 I2C OUTPUT ENABLE...

Page 48: ...e to the I O supply source Ensure that the voltage at the pin does not exceed the I O supply voltage VDDIO VDD and drop below VSS For the absolute maximum and minimum GPIO voltage see the device data...

Page 49: ...quired a 0 must be written to that pin s Data Register Interfacing mechanical switches is a com mon application of these drive modes The resistive modes are also used to interface PSoC with open drain...

Page 50: ...iven by other signals that may cause shorts 7 3 2 2 Slew Rate Control GPIO pins have fast and slow output slew rate options in strong drive mode this is configured using PORT_SLOW bit of the Port Conf...

Page 51: ...ws the status of GPIOs in low power modes 7 7 Interrupt In the PSoC 4 device all the port pins have the capability to generate interrupts As shown in Figure 7 2 the pin signal is routed to the interru...

Page 52: ...tus register is read when an interrupt is occurring on the cor responding port it can result in the interrupt not being properly detected Therefore when using GPIO interrupts it is recommended to read...

Page 53: ...Modulator TCPWM Block TCPWM has dedicated connections to the pin See the device datasheet for details on these dedicated pins of PSoC 4 Note that when the TCPWM block inputs such as start and stop are...

Page 54: ...54 PSoC 4000 Family PSoC 4 Architecture TRM Document No 001 89309 Rev D I O System...

Page 55: ...cy clock HFCLK of up to 48 MHz selected from IMO or external clock Dedicated prescaler for HFCLK Low frequency clock LFCLK sourced by ILO Dedicated prescaler for system clock SYSCLK of up to 16 MHz so...

Page 56: ...the corresponding trim registers CLK_IMO_TRIM1 These values may be loaded at startup to achieve the desired configuration Firmware can retrieve these trim values and reconfigure the device to change...

Page 57: ...reset is not recommended if WDT protection is required against firmware crashes WDT protection is required against the power supply events that produce sudden brownout events that may in turn com prom...

Page 58: ...divide by 1 Note The SYSCLK frequency cannot exceed 16 MHz 8 3 4 Peripheral Clock Divider Configuration The four peripheral clocks are derived from the HFCLK using the 16 bit peripheral clock divider...

Page 59: ...1 as a result of an ENABLE command HW sets this field to 0 as a result on a DISABLE command 7 3 FRAC5_DIV_x Fractional division by FRAC5_DIV 32 Allows for fractional divisions in the range 0 31 32 Not...

Page 60: ...60 PSoC 4000 Family PSoC 4 Architecture TRM Document No 001 89309 Rev D Clocking System...

Page 61: ...different internal regulators to support the various power modes These include Active digital regulator Quiet regu lator and Deep Sleep regulator 1 When the system supply is in the range 1 80 V to 1...

Page 62: ...he other low voltage supplies In direct supply configuration VCCD and VDD must be shorted together and connected to a supply of 1 71 V to 1 89 V The Active digital regulator is still powered up and en...

Page 63: ...works down to 1 8 V In this mode the internal regulator supplies the internal logic The VCCD output must be bypassed to ground via a 0 1 F external ceramic capacitor Bypass capacitors are also require...

Page 64: ...ulator are enabled during the Active or Sleep power modes They are turned off in the Deep Sleep mode see Table 9 1 and Figure 9 1 9 3 1 1 Active Digital Regulator For external supplies from 1 8 V and...

Page 65: ...ts monitor VCCD voltage Typically the POR circuits are not very accurate with respect to trip point POR circuits are used during initial chip power up and then disabled 9 4 1 1 Brownout Detect BOD The...

Page 66: ...66 PSoC 4000 Family PSoC 4 Architecture TRM Document No 001 89309 Rev D Power Supply and Monitoring...

Page 67: ...rmware execution in this mode includes the automatically generated firmware by the PSoC Creator IDE and the firmware written by the user The automatically generated firmware can govern both the firmwa...

Page 68: ...68 PSoC 4000 Family PSoC 4 Architecture TRM Document No 001 89309 Rev D Chip Operational Modes...

Page 69: ...architecture ISA The power consumption in different power modes is controlled by using the following methods Enabling disabling peripherals Powering on off internal regulators Powering on off clock s...

Page 70: ...mains on and low frequency peripher als continue to operate Digital peripherals that do not need a clock or receive a clock from their external interface for exam ple I2C slave continue to operate Int...

Page 71: ...IMO Available Available Not Available Internal low speed oscillator ILO kHz Available Available Available optional Asynchronous peripherals Available Available Available Power on reset Brownout detect...

Page 72: ...ister shows the status of Deep Sleep regulator If the firmware tries to enter Deep Sleep mode before the regulators are ready then PSoC 4 goes to Sleep mode first and when the regulators are ready the...

Page 73: ...WDT interrupt has a programmable period of up to 2048 ms The WDT is a free running wraparound up counter with a maximum of 16 bit resolution The resolution is configurable as explained later in this s...

Page 74: ...pt generator 1 Write the desired IGNORE_BITS in the WDT_MATCH register to set the counter resolution 2 Write the desired match value to the WDT_MATCH register 3 Clear the WDT_MATCH bit in SRSS_INTR to...

Page 75: ...ich will then wake up the CPU The CPU acknowledges the interrupt request and executes the ISR The interrupt must be cleared after entering the ISR in firmware For more details on device power modes se...

Page 76: ...76 PSoC 4000 Family PSoC 4 Architecture TRM Document No 001 89309 Rev D Watchdog Timer...

Page 77: ...g to the datasheet specification The POR activates automatically at power up POR events do not set a reset cause status bit but can be partially inferred by the absence of any other reset source If no...

Page 78: ...Reset Protection fault reset PROT_FAULT detects unauthorized protection violations and causes a device reset if they occur One example of a protection fault is if a debug breakpoint is reached while...

Page 79: ...bservation CPU execution in a privileged mode by use of the non maskable interrupt NMI When in privileged mode NMI remains asserted to prevent any inadvertent return from interrupt instructions causin...

Page 80: ...advertent writes to the bootloader portion of flash Flash memory is organized in rows You can assign one of two protection levels to each row see Table 14 1 Flash protection levels can only be changed...

Page 81: ...on E Digital System This section encompasses the following chapters Inter Integrated Circuit I2C chapter on page 83 Timer Counter and PWM chapter on page 101 Top Level Architecture Digital System Bloc...

Page 82: ...82 PSoC 4000 Family PSoC 4 Architecture TRM Document No 001 89309 Rev D...

Page 83: ...k signal SCL Error reduction using an digital median filter on the input path of the I2C data signal SDA Glitch free signal transmission with an analog glitch filter Interrupt or polling CPU interface...

Page 84: ...r must wait until the current operation is complete before issuing a START signal see Table 15 3 Figure 15 2 and Figure 15 3 The master looks for a STOP signal as an indicator that it can start its da...

Page 85: ...The master then writes a 7 bit I2C slave address and a read indicator 1 after the START condition The addressed slave transmits an acknowledge ment by pulling the data line low during the ninth bit ti...

Page 86: ...rray Write An EZ write to a memory array index is by means of an I2C write transfer The first transmitted write data is used to send an EZ address from the master to the slave The five lowest signific...

Page 87: ...bit in transmission SCB_TX_FIFO_CTRL Specifies the trigger level clearing of the transmitter FIFO and shift registers and FREEZE operation of the transmitter FIFO SCB_TX_FIFO_STATUS Indicates the num...

Page 88: ...sible interrupt sources The interrupt is triggered when any of the enabled interrupt conditions are met Interrupt status registers are used to determine the actual source of the interrupt For more in...

Page 89: ...therefore it is not used for non EZ functionality Internally and externally clocked operations are determined by two register fields of the SCB_CTRL register Table 15 6 SCB_TX_CTRL SCB_RX_CTRL Registe...

Page 90: ...e bit which can be used to generate an interrupt to wakeup the CPU In Active system power mode the CPU is active and the wakeup interrupt cause is disabled associated MASK bit is 0 The externally cloc...

Page 91: ...system power modes when an I2C address match occurs The fixed func tion I2C block performs either of two actions after address match Address ACK or Address NACK Address ACK The I2C slave executes cloc...

Page 92: ...d Function I2C block Select Master mode Enable TX FIFO Enable SCB I2C block Transmission of one byte slave address complete No stretch E Address ACK ed or NACK ed Error Yes NACK STOP RESTART Set Fixed...

Page 93: ...ect Master mode Enable RX FIFO Enable Fixed Function I2C block Transmission of one byte slave address complete No stretch E Address ACK ed or NACK ed Error Yes NACK STOP RESTART Set Fixed Function I2C...

Page 94: ...rt Begin Disable Fixed Function I2C block Select Slave mode Enable TX FIFO Enable Fixed Function I2C block Receiving one byte slave address complete No stretch E Address ACK ed or NACK ed Error Yes NA...

Page 95: ...ct Slave mode Enable RX FIFO Enable Fixed Function I2C block Receiving one byte slave address complete No stretch E Address ACK ed or NACK ed Error Yes NACK Set Fixed Function I2C block to receive mod...

Page 96: ...Flow Chart Transmitting one byte data complete EZ buffer empty Yes Yes E Byte ACK ed or NACK ed ACK No E Error Begin No NACK Data transfer complete No Yes Select transmit mode E Report and handle erro...

Page 97: ...nable Fixed Function I2C block Select EZ mode Receiving one byte slave address complete No stretch E Address ACK ed or NACK ed Error Yes NACK ACK START detected Wake up Receiving one byte data complet...

Page 98: ...5 2 12 1 Multi Master Slave Not Enabled Figure 15 11 Multi Master Slave Not Enabled Flow Chart Begin Disable Fixed Function I2C block Select M aster m ode Enable TX FIFO Enable Fixed Function I2C bloc...

Page 99: ...hart Begin Disable Fixed Function I2C block Select Master and Slave mode Enable TX FIFO Enable Fixed Function I2C block Send START signal Transmission of one byte slave address complete No stretch E B...

Page 100: ...100 PSoC 4000 Family PSoC 4 Architecture TRM Document No 001 89309 Rev D Inter Integrated Circuit I2C...

Page 101: ...udo random PWM PWM with dead time Multiple counting modes up down and up down Clock prescaling division by 1 2 4 64 128 Double buffering of compare capture and period values Supports interrupt on Term...

Page 102: ...TRL Note The counter must be configured before enabling it If the counter is enabled after being configured registers are updated with the new configuration values Disabling the counter retains the va...

Page 103: ...n be used to syn chronize quadrature decoding Start A start event is used to start counting it can be used after a stop event or after re initialization of the counter register to any value by softwar...

Page 104: ...rupt can be generated for a TC con dition or a CC condition The exact definition of these conditions is mode specific All eight interrupt output signals from the eight TCPWMs are also OR ed together t...

Page 105: ...t Line for OV UN and CC Conditions Field Bit Value Event Description CC_MATCH_MODE Default Value 3 1 0 0 Set line_out to 1 Configures output line on a compare match CC event 1 Clear line_out to 0 2 In...

Page 106: ...e counter is decremented or incremented based on two phase inputs according to the selected X1 X2 or X4 encoding scheme PWM 100 Implements edge center aligned PWMs with an 8 bit clock prescaler and bu...

Page 107: ...h 0 In the down counting mode after the count register reaches zero the count register is reloaded with the value in the period register In the up down counting modes the count register value is not u...

Page 108: ...Modes Period TC Counter Timer down counting mode 0xFFFF counter_clock 0xFFFF 0xFFFE 0xFFFD 0xFFFC 0x0001 0x0000 0x0002 0x0003 UN OV 0xFFFF 0xFFFE 0xFFFD 0xFFFC 0x0001 0xFFFF 0xFFFE Period TC Counter T...

Page 109: ...shown in Table 16 1 7 Set the direction of counting by writing to the UP_DOWN_MODE 17 16 field of the TCPWM_CNT_CTRL register as shown in Table 16 6 8 The timer can be configured to run either in cont...

Page 110: ...d either by hardware or software the current count register value is copied to the capture register TCPWM_CNT_CC and the capture register value is copied to the buffer capture register TCPWM_CNT_CC_BU...

Page 111: ...ct Capture mode by writing 010 to the MODE 26 24 field of the TCPWM_CNT_CTRL register 3 Set the required 16 bit period in the TCPWM_CNT_PERIOD register 4 Set clock prescaling by writing to the GENERIC...

Page 112: ...pulse on CC output signal is generated when the count register value reaches 0x0000 or 0xFFFF On a CC con dition the count register is set to the period value 0x8000 in this case On TC or CC condition...

Page 113: ...ter_clock period the phases should not change value more than once The X2 and X4 quadrature encoding modes count twice and four times as fast as the X1 encoding mode Figure 16 10 illustrates the quadr...

Page 114: ...eriod in the TCPWM_CNT_PERIOD register 4 Set the required encoding mode by writing to the QUADRATURE_MODE 21 20 field of the TCPWM_CNT_CTRL register 5 Set the TCPWM_CNT_TR_CTRL0 register to select the...

Page 115: ...nals impact the output line the desired PWM output alignment can be obtained The recommended way to modify the duty cycle is The buffer period register and buffer compare register are updated with new...

Page 116: ...er and compare buffer registers are updated Because the updates of the second PWM pulse come late after the terminal count the first PWM pulse is repeated Note that the switch event is automatically c...

Page 117: ...able 16 3 For right aligned PWM use the down counting mode configure UN condition to reset output line to 0 and CC condition to set the output line to 1 See Table 16 3 16 3 4 4 Kill Feature The kill f...

Page 118: ..._CNT_CC register and buffer compare value in the TCPWM_CNT_CC_BUFF register to switch values if required 6 Set the direction of counting by writing to the UP_DOWN_MODE 17 16 field of the TCPWM_CNT_CTR...

Page 119: ...the dead band period is complete dt_line is set to 1 On the falling edge of the PWM line_out depending upon UN OV and CC conditions the dead time block sets the dt_line and dt_line_compl to 0 The dead...

Page 120: ...s if required 6 Set the direction of counting by writing to the UP_DOWN_MODE 17 16 field of the TCPWM_CNT_CTRL register to con figure left aligned right aligned or center aligned PWM as shown in Table...

Page 121: ...PR Mode Block Diagram 16 3 6 2 How It Works The counter register is used to implement LFSR with the polynomial x16 x14 x13 x11 1 as shown in Figure 16 17 It gener ates all the numbers in the range 1 0...

Page 122: ...Figure 16 18 Timing Diagram for Pseudo Random PWM A capture switch input signal may switch the values between the compare and compare buffer registers and the period and period buffer registers This...

Page 123: ...the value with counter value TCPWM_CNT_CC_BUFF Counter buffered compare capture register Buffer register for counter CC register switches period value TCPWM_CNT_PERIOD Counter period register Contain...

Page 124: ...124 PSoC 4000 Family PSoC 4 Architecture TRM Document No 001 89309 Rev D Timer Counter and PWM...

Page 125: ...tion F Analog System This section encompasses the following chapter CapSense chapter on page 127 Top Level Architecture Analog System Block Diagram High Speed I O Matrix GPIO Pins CapSense 2 IDACs and...

Page 126: ...126 PSoC 4000 Family PSoC 4 Architecture TRM Document No 001 89309 Rev D...

Page 127: ...class SNR High performance sensing across a variety of overlay materials and thicknesses SmartSense auto tuning technology Supports as many as 16 sensors High range proximity sensing Water tolerant op...

Page 128: ...current to digital converter is similar to a sigma delta ADC The output count of the current to digital converter known as raw count is a digital value that is proportional to the sen sor capacitance...

Page 129: ...nfigurations source current to AMUXBUS A or sink current from AMUXBUS A Figure 17 5 shows the switched capacitance configuration for sourcing current to AMUXBUS A Figure 17 4 PSoC 4 GPIO Cell GPIO cel...

Page 130: ...he sigma delta converter maintains the voltage of AMUXBUS A at a constant VREF this process is explained in Sigma Delta Converter on page 131 Figure 17 6 shows the voltage waveform across the sensor c...

Page 131: ...ates switching clock However the final switching clock frequency depends on the CapSense clock generator It has the following output options Direct Uses the output of programmable clock dividers direc...

Page 132: ...IDAC sinking mode is given by equation 16 10 Equation 17 10 Note that raw count values are always positive The hardware parameters such as ICOMP IMOD and FSW should be tuned to optimum values for reli...

Page 133: ...d electrode Depending on how AMUXBUS B is maintained at VREF two different configurations are possible Shield driving using VREF buffer In this configuration a voltage buffer is used to drive AMUXBUS...

Page 134: ...ge using GPIO cell In this configuration a spe cial GPIO cell and a reference comparator is used to charge the CMOD capacitor to VREF This GPIO cell pre charge capability is available only on a fixed...

Page 135: ...7 bit IDACs can connect to GPIOs using AMUXBUS A and AMUXBUS B It is also possible to connect both IDACs to a single AMUXBUS The IDACS can operate in three different modes CSD only mode General purpo...

Page 136: ...136 PSoC 4000 Family PSoC 4 Architecture TRM Document No 001 89309 Rev D CapSense...

Page 137: ...on G Program and Debug This section encompasses the following chapters Program and Debug Interface chapter on page 139 Nonvolatile Memory Programming chapter on page 147 Top Level Architecture Program...

Page 138: ...138 PSoC 4000 Family PSoC 4 Architecture TRM Document No 001 89309 Rev D...

Page 139: ...port DAP acts as the program and debug interface The external programmer or debugger also known as the host communi cates with the DAP of the PSoC 4 target using the two pins of the SWD interface the...

Page 140: ...not DP APnDP bit determines whether the transfer is an AP access 1b1 or a DP access 1b0 c The Read not Write bit RnW controls which direc tion the data transfer is in 1b1 represents a read from the t...

Page 141: ...was successful A WAIT response requires a data phase For a FAULT status the programming operation should be aborted immediately Table 18 2 shows the ACK bit field decoding details Details on WAIT and...

Page 142: ...Registers Table 18 4 lists the main Cortex M0 AP registers that are used for programming and debugging along with the corresponding SWD address bit selections The APnDP bit is always one for AP regis...

Page 143: ...S pin to reset device Execute ARM s connection sequence to acquire SWD port do SWD_LineReset perform a line reset 50 SWDCK clocks with SWDIO high ack Read_DAP IDCODE out ID Read the IDCODE DP register...

Page 144: ...akpoints can be created by using the BKPT instruction in the Cortex M0 The BPU has two types of registers The breakpoint control register CM0_BP_CTRL is used to enable the BPU and store the number of...

Page 145: ...ers in the debug system Debugging the target device is also affected by the overall device protection setting which is explained in the Device Security chapter on page 79 Only the OPEN protected mode...

Page 146: ...146 PSoC 4000 Family PSoC 4 Architecture TRM Document No 001 89309 Rev D Program and Debug Interface...

Page 147: ...the SPCIF to do the actual flash programming operations PSoC 4 flash is programmed using a Program Erase Program PEP sequence The flash cells are all programmed to a known state erased and then the se...

Page 148: ...called from SRAM the SPC timer triggers its interrupt when each of the sub opera tions in a write or program operation is complete Call the Resume Non Blocking function from the SPC interrupt ser vice...

Page 149: ...e Detailed information on each of the system calls follows the table 19 5 1 Silicon ID This function returns a 12 bit family ID 16 bit silicon ID and an 8 bit revision ID and the current device protec...

Page 150: ...7 0 Silicon ID Lo See the device datasheet for Silicon ID values for different part numbers Bits 15 8 Silicon ID Hi Bits 19 16 Minor Revision Id Bits 23 20 Major Revision Id Bits 27 24 0xXX Not used...

Page 151: ...aligned SRAM address Bits 7 0 0xB6 Key1 Bits 15 8 0xD7 Key2 Bits 23 16 Byte Addr Start address of page latch buffer to write data 0x00 Byte 0 of latch buffer 0x3F Byte 63 of latch buffer Bits 31 24 Fl...

Page 152: ...atch buffer If all data in the page latch buffer is 0 then the program is skipped The row must be in an erased state before calling this function It clears the page latch buffer contents after the row...

Page 153: ...r a row of flash and returns the 24 bit sum of each byte read in that flash region When performing a checksum on the whole flash the user code and supervisory flash regions are included When CPUSS_SYS...

Page 154: ...e HF clock clk_hf are set to IMO at 48 MHz The Load Flash Bytes function is used to load the flash protection bytes of a flash macro into the page latch buffer corresponding to the macro The starting...

Page 155: ...are must not attempt to put the device to sleep during a non blocking write row This action will reset the page latch buffer and the flash will be written with all zeroes Usage Requirements Call the C...

Page 156: ...the charge pump clock clk_pump and the HF clock clk_hf are set to IMO at 48 MHz Call the Load Flash Bytes function before calling this function to load the data bytes that will be used for programming...

Page 157: ...hYY 32 bit word aligned address of the SRAM that stores the first function parameter key1 CPUSS_SYSREQ register Bits 15 0 0x0008 Non Blocking Program Row opcode Bits 31 16 0x8000 Set SYSCALL_REQ bit A...

Page 158: ...ither out of bounds or the size pro vided is too large for the page address F0000004h Invalid Address The row ID or byte address provided is outside of the available memory F0000005h Row Protected The...

Page 159: ...am int iStatusInt 0x00 __flash int main void DoUserStuff CM0 interrupt enable bit for spc interrupt enable CM0_ISER_REG 0x00000040 Set CPUSS_CONFIG VECS_IN_RAM because SPC ISR should be in SRAM CPUSS_...

Page 160: ...Q_REG 0x80000007 Execute user code until iStatusInt equals 3 to signify 3 SPC interrupts have happened This should be 1 in case of non blocking program System Call while iStatusInt 0x03 DoOtherUserStu...

Page 161: ...ss The label or number identifying the memory location RAM ROM or register where a unit of information is stored algorithm A procedure for solving a mathematical problem in a finite number of steps th...

Page 162: ...y irrespective of any clock sig nal attenuation The decrease in intensity of a signal as a result of absorption of energy and of scattering out of the path to the detector but not including the reduct...

Page 163: ...ten use for example A B for OR and for AND for example A B in some ways those operations are analogous to addition and multiplication in other algebraic structures and represent NOT by a line drawn ab...

Page 164: ...comparator An electronic circuit that produces an output voltage or current whenever two input levels simul taneously satisfy predetermined amplitude requirements compiler A program that translates a...

Page 165: ...alue or action a sys tem will assume use or take in the absence of instructions from the user device The device referred to in this manual is the PSoC device unless otherwise specified die An non pack...

Page 166: ...Flash block The smallest amount of flash ROM space that may be programmed at one time and the smallest amount of flash space that may be protected A flash block holds 64 bytes flip flop A device havi...

Page 167: ...as two consecutive hexadecimal digits Compare the binary hex and decimal representations bin hex dec 0000b 0x0 0 0001b 0x1 1 0010b 0x2 2 1001b 0x9 9 1010b 0xA 10 1011b 0xB 11 1111b 0xF 15 So the decim...

Page 168: ...er program caused by an event external to that process and performed in such a way that the process can be resumed interrupt service rou tine ISR A block of code that normal code execution is diverted...

Page 169: ...macro instance with the macro contents when an instance of the macro is encountered Therefore if a macro is used five times and the macro definition required 10 bytes of code space 50 bytes of code sp...

Page 170: ...is made by using an upper case B for byte in MSB multiplexer mux 1 A logic function that uses a binary value or address to select between a number of inputs and conveys the data from the selected inpu...

Page 171: ...nouts The pin number assignment the relation between the logical inputs and outputs of the PSoC device and their physical counterparts in the printed circuit board PCB package Pinouts will involve pin...

Page 172: ...device from which data can be read out but new data cannot be written in routine A block of code called by another block of code that may have some general or frequent use routing Physically connecti...

Page 173: ...out the operation of a data processing system for example compilers library routines manuals and circuit diagrams Software is often written first as source code and then converted to a binary format t...

Page 174: ...istive voltage divider terminal count The state at which a counter is counted down to zero threshold The minimum value of a signal that can be detected by the system or sensor under consider ation Thu...

Page 175: ...y to be modified during normal program execution and not just during initialization Registers in bank 1 are most likely to be modified only during the initialization phase of the program V VDDD A name...

Page 176: ...Index 176 PSoC 4000 Family PSoC 4 Architecture TRM Document No 001 89309 Rev D...

Page 177: ...et 78 F features I O system 45 watchdog timer 73 G glossary 161 GPIO pins in creation of buttons and sliders 53 H high impedance analog drive mode 49 high impedance digital drive mode 49 I I O drive m...

Page 178: ...ts 13 R register summary I O system 53 registers Cortex M0 27 regulator internal 61 reset identifying sources 78 introduction 77 reset sources description 77 revision history 11 S sleep mode 70 slew r...

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