CY3210-PSoCEVAL1 PSoC® 1 Evaluation Kit Guide, Doc. #: 001-66768 Rev. *F
44
Code Examples
Figure 5-25. Global Resources Window
Note
a. The clock divider VC1 provides a 3-MHz sample clock to the ADCINC, resulting in a sample
rate of 180 samples per second.
b. The clock divider VC3 generates the baud clock for UART by dividing 24 MHz by 156. The
UART internally divides UART clock (VC3 in this example) by 8, resulting in a baud rate of
19200 bits per second. See the UART UM data sheet for details.
27.Open the existing
main.c
file in Workspace Explorer. Replace the existing
main.c
content with the
content of the embedded
My_First_Example_Project_Main.c
file, which is available within the
attachments feature of this PDF document.
Figure 5-26. Workspace Explorer Window
