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Cypress EZ-USB CX3  

EZ-USB® CX3 Technical Reference Manual, Doc. No. 001-91492 Rev. *B 

22 

1.10.7   

CX3_CSI_SENSOR_SIG_VAL (Register Address: 0x0014) 

This register configures the drive value for the XSHUTDOWN and XRESET signals for the MIPI CSI-2 block. 

This register is set using the 

CyU3PMipicsiSetSensorControl()

 

API. 

BIT 

15 

14 

13 

12 

11 

10 

9 

8 

NAME 

RESERVED 

BIT 

7 

6 

5 

4 

3 

2 

1 

0 

NAME 

RESERVED 

XSHUTDOWN 

OUTPUT 

XRESET 

OUTPUT 

RESERVED 

 

Register Field 

Bit 

Description 

RESERVED 

[15:3] 

RESERVED. Firmware must preserve their settings by reading them, changing 
non-reserved bits, and re-writing them. 

XSHUTDOWN 
OUTPUT 

[2] 

Drive MIPI CSI-2 XSHUTDOWN Signal:  

0: Drive XSHUTDOWN LOW.  

1: Drive XSHUTDOWN HIGH.  

The signal is only driven when 

CX3_CSI_SENSOR_SIG_EN (Register 

Address: 0x0010)

 [2] is 0. 

XRESET OUTPUT 

[1] 

Drive MIPI CSI-2 XRESET Signal:  

0: Drive XRESET LOW.  

1: Drive XRESET HIGH.  

The signal is only driven when 

CX3_CSI_SENSOR_SIG_EN (Register 

Address: 0x0010)

 [1] is 0. 

RESERVED 

[0] 

RESERVED. Firmware must preserve their settings by reading them, changing 
non-reserved bits, and re-writing them. 

 

Summary of Contents for EZ-USB CX3

Page 1: ...EZ USB CX3 Technical Reference Manual Supplement to the EZ USB FX3 Technical Reference Manual Doc No 001 91492 Rev B...

Page 2: ...0 fps or 720p at 60 fps CX3 supports a wide variety of image formats including RAW8 10 12 14 YUV422 RGB888 666 565 and user defined 8 bit Figure 1 EZ USB CX3 Device Based on the proven EZ USB FX3 plat...

Page 3: ...S FS LS OTG Host SS Peripheral HS FS Peripheral Charger Detection EZ Dtect USB Interface ARM926EJ S JTAG System RAM I2 C_SDA I2 C_SCL D D SSTX SSTX SSRX SSRX OTG_ID FX3 BLOCK DIAGRAM Memory Controller...

Page 4: ...PI Master Yes Yes UART Yes Yes I2 C Master Controller Yes Yes U Port Support USB 3 0 Peripheral Yes Yes USB 2 0 Peripheral Yes Yes 32 Physical endpoints Yes Yes Charger Detection 1 1 Support EZ Dtect...

Page 5: ...1 Revision 0 04 April 2 2009 o Supports up to four data lanes each lane supports up to 1 Gbps o Camera Control Interface over I2 C support for image sensor configuration Supports the following video d...

Page 6: ...2 C bus 2 The CX3 MIPI CSI 2 receiver block reads the data from the image sensor de serializes it merges lanes de packetizes it and then sends it as a parallel input to the fixed function GPIF II bloc...

Page 7: ...CSI 2 block CyU3PMipicsiQueryIntfParams API to query settings from the MIPI CSI 2 block CyU3PMipicsiSleep API to place the MIPI CSI 2 block in the low power sleep mode CyU3PMipicsiWakeup API to wake t...

Page 8: ...s up to 1 Gbps per lane The MIPI CSI 2 receiver is connected to a fixed function GPIF II controller via an 8 16 or 24 bit data bus which can be clocked up to 100 MHz The maximum bandwidth that can be...

Page 9: ...2 b0 RAW 13 0 RGB888 CY_U3P_CSI_DF_RGB888 RGB 888 format 24 bits per pixel 0x24 24 bit R 7 0 G 7 0 B 7 0 RGB666 Mode 0 CY_U3P_CSI_DF_RGB666_0 RGB 666 format 24 bits per pixel 0x23 24 bit 2 b0 R 5 0 2...

Page 10: ...ed is larger than the width of the output stream for example if a 24 bit GPIF II bus width is used for the CY_U3P_CSI_DF_YUV422_8_1 type the upper bits on the GPIF II are padded with 0s For stream for...

Page 11: ...n the following sections 1 7 1 Reference Clock REFCLK This is the reference clock input provided to the MIPI CSI 2 block This input clock should be between 6 and 40 MHz 1 7 2 PLL Clock PLL_CLK The PLL...

Page 12: ...enerated by dividing the PLL_CLK by a value of 2 4 or 8 The maximum value for this clock is 100 MHz This clock frequency is calculated automatically by the MIPI Receiver configuration tool 1 7 5 Image...

Page 13: ...on the MIPI CSI 2 block are stopped and there will be no data transfer All register settings are retained in this state Soft Reset This state puts the MIPI CSI 2 block into reset mode where all clock...

Page 14: ...ffer in thread 0 Intr CPU Frame end full buffer in thread 1 Intr CPU Frame end partial buffer in thread 0 Intr CPU Frame end partial buffer in thread 1 Intr CPU FV FV LV LV DATA Limit LV ADDR Limit LV...

Page 15: ...Name Description 0x0002 CX3_SYSTEM_CTRL System Control Register 0x0004 CX3_CONFIG_CTRL Configuration Control Register 0x0006 CX3_FIFO_CTRL FIFO Control register 0x0008 CX3_DATA_FMT Data Format Control...

Page 16: ...et APIs BIT 15 14 13 12 11 10 9 8 NAME RESERVED BIT 7 6 5 4 3 2 1 0 NAME RESERVED SLEEP RESET Register Field Bit Description RESERVED 15 2 RESERVED Firmware must preserve their settings by reading the...

Page 17: ...DATA_FMT register The combination of DATA MODE and the DATA FORMAT is used to select the output stream as defined in Table 3 The DATA FORMAT setting determines the output data format while the DATA MO...

Page 18: ...ransferring data to GPIF II interface This register is set by the CyU3PMipicsiSetIntfParams API and queried using the CyU3PMipicsiQueryIntfParams API BIT 15 14 13 12 11 10 9 8 NAME RESERVED FIFO LEVEL...

Page 19: ...Selection Selects the output data format 4 b0000 RAW8 4 b0001 RAW10 4 b0010 RAW12 4 b0011 RGB888 4 b0100 RGB666 4 b0101 RGB565 4 b0110 YUV422 8 bit 4 b0111 RESERVED 4 b1000 RAW14 4 b1001 YUV422 10 bi...

Page 20: ...s register is set by the CyU3PMipicsiSetIntfParams API and queried using the CyU3PMipicsiQueryIntfParams API BIT 15 14 13 12 11 10 9 8 NAME MCLK HIGH BIT 7 6 5 4 3 2 1 0 NAME MCLK LOW Register field B...

Page 21: ...rve their settings by reading them changing non reserved bits and re writing them XSHUTDOWN ENABLE 2 Enable MIPI CSI 2 XSHUTDOWN Signal 0 Enables the output for the MIPI CSI 2 XSHUTDOWN signal 1 Disab...

Page 22: ...ter Field Bit Description RESERVED 15 3 RESERVED Firmware must preserve their settings by reading them changing non reserved bits and re writing them XSHUTDOWN OUTPUT 2 Drive MIPI CSI 2 XSHUTDOWN Sign...

Page 23: ...is set by the CyU3PMipicsiSetIntfParams API and queried using the CyU3PMipicsiQueryIntfParams API BIT 15 14 13 12 11 10 9 8 NAME PLL PRD RESERVED PLL FBD 8 BIT 7 6 5 4 3 2 1 0 NAME PLL FBD 7 0 Registe...

Page 24: ...ust preserve their settings by reading them changing non reserved bits and re writing them PLL FRS 11 10 Frequency Range Selection Determines the PLL frequency range See Section 1 7 2 for details on t...

Page 25: ...Divider for CSI RX LP HS Transition Clock Divides down from the PLL clock to generate this clock See Section 1 7 3 for details 2 b00 PLL CLOCK 8 2 b01 PLL CLOCK 4 2 b10 PLL CLOCK 2 2 b00 RESERVED This...

Page 26: ...fParams API BIT 15 14 13 12 11 10 9 8 NAME BYTE COUNT 15 8 TYPE R W BIT 7 6 5 4 3 2 1 0 NAME BYTE COUNT 7 0 TYPE R W Register Field Bit Description BYTE COUNT 15 0 Total number of bytes per Line Numbe...

Page 27: ...C TERM RESERVED BIT 7 6 5 4 3 2 1 0 NAME TD TERM THS SETTLE Register Field Bit Description TC TERM 15 TC TERM Selection Set to 1 for normal operation 0 is not supported RESERVED 14 8 RESERVED Firmware...

Page 28: ...egister in its default state 0x0000 thereby setting the MIPI XRESET and XSHUTDOWN signals to Drive LOW If either of these signals needs to be in Drive HIGH state for sensor operation it needs to be ex...

Page 29: ...tion does not return 1 11 5 CyU3PMipicsiSleep CyU3PReturnStatus_t CyU3PMipicsiSleep void This function is used to disable the PLL clocks on the MIPI CSI 2 block and place it in low power sleep No data...

Page 30: ...is function sets the following MIPI CSI 2 block registers with values from the CyU3PMipicsiCfg_t structure passed to it as shown in Table 6 Table 6 Parameters Used for Configuring MIPI CSI 2 Block Reg...

Page 31: ...should be initialized prior to being passed to this function 1 11 12 CyU3PMipicsiGpifLoad CyU3PReturnStatus_t CyU3PMipicsiGpifLoad CyU3PMipicsiBusWidth_t busWidth uint32 t bufferSize As described in S...

Page 32: ...3 including Datasheets Application notes and the EZ USB FX3 Technical Reference Manual TRM can be found at http www cypress com fx3 The EZ USB FX3 SDK software download and documentation provided as p...

Page 33: ...tion 1 9 of this TRM supplement More details can be found in the General Programmable Interface II GPIF II chapter of the EZ USB FX3 TRM I2 C The I2 C bus protocol created by Philips Semiconductor sta...

Page 34: ...nt to be changed by the user When writing to a register with RESERVED bits you should ensure that the values are not changed during a Write preferably by doing a Read before the Write and maintaining...

Page 35: ...NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE No computing device can be absolutely secure Therefore despite security measures implemented in Cypress h...

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