Cypress EZ-BLE PSoC CYBLE-224116-01 Manual Download

Page: 11 / 47

CYBLE-224116-01

Document Number: 002-12524 Rev. *D

Page 11 of 47

Table 5. Analog Peripheral Capabilities

Pad Number

Device Port Pin

SARMUX

OPAMP

LPCOMP

GND

[6]

Ground Connection

XRES

External Reset Hardware Connection Input

P1.5

✓

(CTBm1_OA1_INP)

P1.1

✓

(CTBm1_OA0_INN)

P1.0

✓

(CTBm1_OA0_INP)

P0.1

P0.4

✓

(COMP1_INP)

P0.5

✓

(COMP1_INN)

P0.7

P1.3

✓

(CTBm1_OA1_OUT)

DDR

Radio Power Supply (2.0 V to 3.6 V)

P0.6

P1.2

✓

(CTBm1_OA0_OUT)

VDD

Digital Power Supply Input (2.0 V to 3.6 V)

P1.4

✓

(CTBm1_OA1_INN)

P2.1

✓

(CTBm0_OA0_INN)

DDA

Analog Power Supply Input (2.0 V to 3.6 V)

P2.2

✓

(CTBm0_OA0_OUT)

P2.6

✓

(CTBm0_OA0_INP)

P3.0

✓

P2.3

✓

(CTBm0_OA1_OUT)

VREF

Reference Voltage Input (Optional)

P3.4

✓

P3.5

✓

P3.7

✓

P3.1

✓

P3.6

✓

P2.5

✓

(CTBm0_OA1_INP)

P5.0

P5.1

P2.4

✓

(CTBm0_OA1_INN)

GND

Ground Connection

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Summary of Contents for EZ-BLE PSoC CYBLE-224116-01

Page 1: ...esolution 1 Second connection interval with PA LNA active 26 3 µA TX current consumption BLE silicon 15 6 mA radio only 0 dBm SE2438T 20 mA PA LNA only 9 5 dBm RX current consumption of 16 4 mA radio only BLE silicon 16 4 mA radio only SE2438T 5 5 mA PA LNA only Low power mode support Deep Sleep 1 3 µA with watch crystal oscillator WCO on Hibernate 150 nA with SRAM retention Stop 60 nA with XRES w...

Page 2: ... Creator is an Integrated Design Environment IDE that enables concurrent hardware and firmware editing compiling and debugging of PSoC 3 PSoC 4 PSoC 5LP PSoC 4 BLE PRoC BLE and EZ BLE module systems with no code size limitations PSoC peripherals are designed using schematic capture and simple graphical user interface GUI with over 120 pre verified production ready PSoC Components PSoC Components a...

Page 3: ...Communication 28 Memory 29 System Resources 29 Environmental Specifications 35 Environmental Compliance 35 RF Certification 35 Safety Certification 35 Environmental Conditions 35 ESD and EMI Protection 35 Regulatory Information 36 FCC 36 Innovation Science and Economic Development ISED Canada Certification 37 European Declaration of Conformity 38 MIC Japan 38 KC Korea 38 Packaging 39 Ordering Info...

Page 4: ... the physical dimensions shown in the mechanical drawings in Figure 1 All dimensions are in millimeters mm Table 1 Module Design Dimensions See Figure 1 on page 5 for the mechanical reference drawing for CYBLE 224116 01 Dimension Item Specification Module dimensions Length X 9 50 0 15 mm Width Y 15 40 0 15 mm Antenna location dimensions Length X 7 00 mm Width Y 5 00 mm PCB thickness Height H 0 50 ...

Page 5: ...al should be located beneath or above the antenna area Only bare PCB material should be located beneath the antenna area For more information on recommended host PCB layout see Figure 3 Figure 4 Figure 5 and Figure 6 and Table 3 Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com ...

Page 6: ...l the solder pad length width and pitch dimensions of the CYBLE 224116 01 module Figure 2 Solder Pad Dimensions Seen from Bottom Table 2 Solder Pad Connection Description Name Connections Connection Type Pad Length Dimension Pad Width Dimension Pad Pitch SP 32 Solder Pads 0 71 mm 0 41 mm 0 76 mm Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com...

Page 7: ...formance the area immediately around the Cypress BLE module chip antenna should contain an additional keep out area where no grounding or signal traces are contained The keep out area applies to all layers of the host board The recommended dimensions of the host PCB keep out area are shown in Figure 3 dimensions are in mm Figure 3 Recommended Host PCB Keep Out Area Around the CYBLE 224116 01 Chip ...

Page 8: ...d to either side is recommended as shown in Figure 6 The host PCB layout pattern can be completed using either Figure 4 Figure 5 or Figure 6 It is not necessary to use all figures to complete the host PCB layout pattern Figure 4 Host Layout Pattern for CYBLE 224116 01 Figure 5 Module Pad Location from Origin Top View Seen on Host PCB Top View Seen on Host PCB Downloaded from Arrow com Downloaded f...

Page 9: ... 11 2 08 15 14 81 89 596 06 12 2 84 15 14 111 81 596 06 13 3 61 15 14 142 13 596 06 14 4 37 15 14 172 13 596 06 15 5 13 15 14 202 13 596 06 16 5 89 15 14 231 89 596 06 17 6 65 15 14 261 81 596 06 18 7 42 15 14 292 13 596 06 19 8 18 15 14 322 05 596 06 20 8 94 15 14 351 97 596 06 21 9 24 14 04 363 78 552 76 22 9 24 13 28 363 78 522 83 23 9 24 12 51 363 78 492 52 24 9 24 11 75 363 78 462 60 25 9 24 ...

Page 10: ... 2 0 V to 3 6 V 15 P1 4 SCB0_RX SCB0_MOSI SCB0_SDA TCPWM 16 P2 1 SCB0_SS2 TCPWM 17 VDDA Analog Power Supply Input 2 0 V to 3 6 V 18 P2 2 SCB0_SS3 TCPWM 19 P2 6 TCPWM 20 P3 0 SCB0_RX SCB0_SDA TCPWM 21 P2 3 TCPWM 22 VREF Reference Voltage Input 23 P3 4 SCB1_RX SCB1_SDA TCPWM 24 P3 5 SCB1_TX SCB1_SCL TCPWM 25 P3 7 SCB1_CTS TCPWM 26 P3 1 SCB0_TX SCB0_SCL TCPWM 27 P3 6 SCB1_RTS TCPWM 28 P2 5 TCPWM 29 P...

Page 11: ...r Supply Input 2 0 V to 3 6 V 15 P1 4 CTBm1_OA1_INN 16 P2 1 CTBm0_OA0_INN 17 VDDA Analog Power Supply Input 2 0 V to 3 6 V 18 P2 2 CTBm0_OA0_OUT 19 P2 6 CTBm0_OA0_INP 20 P3 0 21 P2 3 CTBm0_OA1_OUT 22 VREF Reference Voltage Input Optional 23 P3 4 24 P3 5 25 P3 7 26 P3 1 27 P3 6 28 P2 5 CTBm0_OA1_INP 29 P5 0 30 P5 1 31 P2 4 CTBm0_OA1_INN 32 GND Ground Connection Downloaded from Arrow com Downloaded ...

Page 12: ...tely External Component Recommendation In either connection scenario it is recommended to place an external ferrite bead between the supply and the module connection The ferrite bead should be positioned as close as possible to the module pin connection Figure 7 details the recommended host schematic options for a single supply scenario The use of one or three ferrite beads will depend on the spec...

Page 13: ...tion Seen from Bottom Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com ...

Page 14: ...nloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com ...

Page 15: ...ystal Y1 24 000 MHz 10PF Crystal Y2 32 768 kHz 12 5PF Item Description Chip Antenna Manufacturer Johanson Technology Inc Chip Antenna Part Number 2450AT18B100 Frequency Range 2400 2500 MHz Peak Gain 0 5 dBi typical Average Gain 0 5 dBi typical Return Loss 9 5 dB minimum Item Description PA LNA Manufacturer Skyworks Inc PA LNA Part Number SE2438T Power Supply Range 2 0 V 3 6 V Parameter Symbol Test...

Page 16: ...tion in the component configuration should be unchecked as these are Firmware GPIOs 3 To configure the CPS and CSD pins open your project s Design Wide Resources file for example Project_Name cydwr from your Workspace Explorer and click the Pins tab The Pins tab is used to select the physical device connections for the outputs CPS CSD These pins are connected to the enable pins of the Skyworks SE2...

Page 17: ...Mode 1 PA LNA commands are both shown 2 When the BLE system is transitioning to Active mode i e waking from low power mode and extended range functionality is required it is necessary to enable the PA LNA to Power Mode 3 Enabling the PA LNA should be the first action completed during when transitioning the PSoC 4 BLE silicon device from a low power mode to active mode Enabling the PA LNA to Power ...

Page 18: ...e 3 5 0 9 5 dBm Configurable via register settings PA active RFO2 6 dBm PA LNA active RFO2 RF output power on ANT PA bypassed 18 0 3 dBm PSoC 4 BLE Silicon Config urable via register settings PA in bypass mode RXS1 RF receive sensitivity on ANT LNA active 95 dBm Measured value RXS2 RF receive sensitivity on ANT LNA bypassed 87 dBm Measured value FR Module frequency range 2402 2480 MHz GP Peak gain...

Page 19: ...d reset active nA T 40 C to 105 C Stop Mode VDD VDDR 2 0 V to 3 6 V PA LNA in All Off IDD33 Stop mode current VDD 20 nA T 25 C VDD 3 3 V IDD34 Stop mode current VDDR 540 nA T 25 C VDDR 3 3 V IDD35 Stop mode current VDD nA T 40 C to 105 C IDD36 Stop mode current VDDR nA T 40 C to 105 C VDDR 2 0 V to 3 6 V Parameter Description Min Typ Max Units Details Conditions FCPU CPU frequency DC 48 MHz 2 0 V ...

Page 20: ... leakage current absolute value 2 nA 25 C VDD 3 3 V IIL_CTBM Input leakage on CTBm input pins 4 nA CIN Input capacitance 7 pF VHYSTTL Input hysteresis LVTTL 25 40 mV 2 7 V VDD 3 6 V VHYSCMOS Input hysteresis CMOS 0 05 VDD 1 IDIODE Current through protection diode to VDD VSS 100 µA ITOT_GPIO Maximum total source or sink chip current 200 mA Downloaded from Arrow com Downloaded from Arrow com Downloa...

Page 21: ... VIH 3 0 V VOL Output voltage LOW level 0 4 V IOL 20 mA VDD 2 9 V Table 18 OVT GPIO AC Specifications P5_0 and P5_1 Only Parameter Description Min Typ Max Units Details Conditions TRISE_OVFS Output rise time in Fast Strong mode 1 5 12 ns 25 pF load 10 90 VDD 3 3 V TFALL_OVFS Output fall time in Fast Strong mode 1 5 12 ns 25 pF load 10 90 VDD 3 3 V TRISESS Output rise time in Slow Strong mode 10 60...

Page 22: ...A IOUT_MAX_LO Power low 5 mA VOUT VDDA 2 7 V VOUT_1 Power high ILOAD 10 mA 0 5 VDDA 0 5 V VOUT_2 Power high ILOAD 1 mA 0 2 VDDA 0 2 V VOUT_3 Power medium ILOAD 1 mA 0 2 VDDA 0 2 V VOUT_4 Power low ILOAD 0 1 mA 0 2 VDDA 0 2 V VOS_TR Offset voltage trimmed 1 0 5 1 mV High mode VOS_TR Offset voltage trimmed 1 mV Medium mode VOS_TR Offset voltage trimmed 2 mV Low mode VOS_DR_TR Offset voltage drift tr...

Page 23: ...Max Units Details Conditions VOFFSET1 Input offset voltage Factory trim 10 mV VOFFSET2 Input offset voltage Custom trim 6 mV VOFFSET3 Input offset voltage ultra low power mode 12 mV VHYST Hysteresis when enabled 10 35 mV VICM1 Input common mode voltage in normal mode 0 VDD 0 1 V Modes 1 and 2 VICM2 Input common mode voltage in low power mode 0 VDD V VICM3 Input common mode voltage in ultra low pow...

Page 24: ...ls single ended 8 8 full speed 10 A CHNKS_D Number of channels differential 4 Diff inputs use neighboring I O 10 A MONO Monotonicity Yes A_GAINERR Gain error 0 1 With external reference A_OFFSET Input offset voltage 2 mV Measured with 1 V VREF A_ISAR Current consumption 1 mA A_VINS Input voltage range single ended VSS VDDA V A_VIND Input voltage range differential VSS VDDA V A_INRES Input resistan...

Page 25: ... operation 2 0 3 6 V IDAC1 DNL for 8 bit resolution 1 1 LSB IDAC1 INL for 8 bit resolution 3 3 LSB IDAC2 DNL for 7 bit resolution 1 1 LSB IDAC2 INL for 7 bit resolution 3 3 LSB SNR Ratio of counts of finger to noise 5 Ratio Capacitance range of 9 pF to 35 pF 0 1 pF sensitivity Radio is not operating during the scan IDAC1_CRT1 Output current of IDAC1 8 bits in High range 612 µA IDAC1_CRT2 Output cu...

Page 26: ... at 12 MHz 130 µA 16 bit counter ICTR3 Block current consumption at 48 MHz 535 µA 16 bit counter Table 30 Counter AC Specifications Parameter Description Min Typ Max Units Details Conditions TCTRFREQ Operating frequency FCLK 48 MHz TCTRPWINT Capture pulse width internal 2 TCLK ns TCTRPWEXT Capture pulse width external 2 TCLK ns TCTRES Counter Resolution TCLK ns TCENWIDINT Enable pulse width intern...

Page 27: ... Typ Max Units Details Conditions ILCDLOW Operating current in low power mode 17 5 µA 16 4 small segment display at 50 Hz CLCDCAP LCD capacitance per segment common driver 500 5000 pF LCDOFFSET Long term segment offset 20 mV ILCDOP1 LCD system operating current VBIAS 3 3 V 2 mA 32 4 segments 50 Hz at 25 C Table 34 LCD Direct Drive AC Specifications Parameter Description Min Typ Max Units Details C...

Page 28: ... Master Mode AC Specifications Parameter Description Min Typ Max Units Details Conditions TDMO MOSI valid after SCLK driving edge 18 ns TDSI MISO valid before SCLK capturing edge Full clock late MISO sampling used 20 ns Full clock late MISO sampling THMO Previous MOSI data hold time 0 ns Referred to Slave capturing edge Table 42 Fixed SPI Slave Mode AC Specifications Parameter Description Min Typ ...

Page 29: ... C FRET3 Flash retention TA 105 C 10 K P E cycles 3 years For TA 85 C Table 45 POR DC Specifications Parameter Description Min Typ Max Units Details Conditions VRISEIPOR Rising trip voltage 0 80 1 45 V VFALLIPOR Falling trip voltage 0 75 1 40 V VIPORHYST Hysteresis 15 200 mV Table 46 POR AC Specifications Parameter Description Min Typ Max Units Details Conditions TPPOR_TR Precision power on reset ...

Page 30: ...on Min Typ Max Units Details Conditions TMONTRIP Voltage monitor trip time 1 µs Table 51 SWD Interface Specifications Parameter Description Min Typ Max Units Details Conditions F_SWDCLK1 3 3 V VDD 3 6 V 14 MHz SWDCLK 1 3 CPU clock frequency F_SWDCLK2 2 0 V VDD 3 3 V 7 MHz SWDCLK 1 3 CPU clock frequency T_SWDI_SETUP T 1 f SWDCLK 0 25 T ns T_SWDI_HOLD T 1 f SWDCLK 0 25 T ns T_SWDO_VALID T 1 f SWDCLK...

Page 31: ...PTRIM_REG Table 57 UDB AC Specifications Parameter Description Min Typ Max Units Details Conditions Data Path performance FMAX TIMER Max frequency of 16 bit timer in a UDB pair 48 MHz FMAX ADDER Max frequency of 16 bit adder in a UDB pair 48 MHz FMAX_CRC Max frequency of 16 bit CRC PRS in a UDB pair 48 MHz PLD Performance in UDB FMAX_PLD Max frequency of 2 pass PLD function in a UDB pair 48 MHz Cl...

Page 32: ...V LE CA 04 C OBB2 Out of band blocking Wanted signal at 67 dBm and Interferer at F 2003 2399 MHz 16 dBm RF PHY Specification RCV LE CA 04 C OBB3 Out of band blocking Wanted signal at 67 dBm and Interferer at F 2484 2997 MHz 16 dBm RF PHY Specification RCV LE CA 04 C OBB4 Out of band blocking Wanted signal a 67 dBm and Interferer at F 3000 12750 MHz 16 dBm RF PHY Specification RCV LE CA 04 C IMD In...

Page 33: ...fications IRX Receive current in normal mode 18 7 mA Silicon Radio only PA LNA disabled IRX_RF Radio receive current in normal mode 16 4 mA Silicon Radio only PA LNA disabled IRX HIGHGAIN Receive current in high gain mode 21 5 mA Silicon Radio only PA LNA disabled ITX 3dBm TX current at 3 dBm setting PA10 20 mA Silicon Radio only PA LNA disabled ITX 0dBm TX current at 0 dBm setting PA7 16 5 mA Sil...

Page 34: ...DLE to BLE RX transition time 75 120 µs RSSI Specifications RSSI ACC RSSI accuracy 5 dB RSSI RES RSSI resolution 1 dB RSSI PER RSSI sample period 6 µs Table 58 BLE Subsystem continued Parameter Description Min Typ Max Units Details Conditions Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com D...

Page 35: ...otocol must be followed in manufacturing to ensure component reliability Description Minimum Specification Maximum Specification Operating temperature 40 C 105 C Operating humidity relative non condensation 5 85 Thermal ramp rate 3 C minute Storage temperature 40 C 110 C Storage temperature and humidity 110 C at 85 ESD Module integrated into system Components 12 15 kV Air 2 2 kV Contact Note 12 Th...

Page 36: ...case the end product must be labeled exterior with Contains FCC ID WAP4110 ANTENNA WARNING This device is tested with a standard SMA connector and with the antenna listed in Table 7 on page 15 When integrated in the OEMs product these fixed antennas require installation preventing end users from replacing them with non approved antennas Any antenna not in the following table must be tested to comp...

Page 37: ...onditions 1 this device may not cause interference and 2 this device must accept any interference including interference that may cause undesired operation of the device Cet appareil est conforme à la norme sur l innovation la science et le développement économique ISED norme RSS exempte de licence L exploitation est autorisée aux deux conditions suivantes 1 l appareil ne doit pas produire de brou...

Page 38: ...end product End product can display the certification label of the embedded module KC Korea CYBLE 224116 01 is certified for use in Korea with certificate number MSIP CRM Cyp 4110 Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded f...

Page 39: ...rrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com D...

Page 40: ...ow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Dow...

Page 41: ...00 unit reel quantities Minimum Order Quantity MOQ 500 Order Increment OI 500 U S Cypress Headquarters Address 198 Champion Court San Jose CA 95134 U S Cypress Headquarter Contact Info 408 943 2600 Cypress website address http www cypress com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com D...

Page 42: ... HVI high voltage interrupt see also LVI LVD IC integrated circuit IDAC current DAC see also DAC VDAC IDE integrated development environment I2C or IIC Inter Integrated Circuit a communications protocol IC Industry Canada IIR infinite impulse response see also FIR ILO internal low speed oscillator see also IMO IMO internal main oscillator see also ILO INL integral nonlinearity see also DNL I O inp...

Page 43: ... static random access memory SRES software reset STN super twisted nematic SWD serial wire debug a test protocol SWV single wire viewer TD transaction descriptor see also DMA THD total harmonic distortion TIA transimpedance amplifier TN twisted nematic TRM technical reference manual TTL transistor transistor logic TUV Germany Technischer Ðúberwachungs Verein Technical Inspection Association TX tra...

Page 44: ...aded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from ...

Page 45: ...o 16 dBm Update OBB2 typical specification parameter from TBD to 16 dBm Update OBB3 typical specification parameter from TBD to 16 dBm Update OBB4 typical specification parameter from TBD to 16 dBm Update IMD typical specification parameter from TBD to 26 dBm Update RXSE1 maximum specification parameter from TBD to 57 dBm Update RXSE2 maximum specification parameter from TBD to 47 dBm Update TXSE1...

Page 46: ...12 Document Title CYBLE 224116 01 EZ BLE PSoC XT XR BT 4 2 Module Document Number 002 12524 Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow ...

Page 47: ...stallations life support devices or systems other medical devices or systems including resuscitation equipment and surgical implants pollution control or hazardous substances management or other uses where the failure of the device or system could cause personal injury death or property damage Unintended Uses A critical component is any component of a device or system whose failure to perform can ...

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