enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H
39
RAM Paging
to the
PSoC Designer Assembly Language User Guide
for
more information on all M8C instructions.
Stack memory accesses are a special case. If they were not,
the stack could fragment across several pages. To prevent
the stack from fragmenting, all instructions that operate on
the stack automatically use the page indicated by the
STK_PP register. Therefore, if the program encounters a
CALL, the enCoRe V device automatically pushes the pro-
gram counter onto the stack page indicated by STK_PP.
After the program counter is pushed, the SRAM paging
mode automatically switches back to the precall mode. All
other stack operations, such as
RET
and
POP
, follow the
same rule as
CALL
. The stack is confined to a single SRAM
page and the Stack Pointer wraps from 00h to FFh and FFh
to 00h. The user code must ensure that the stack is not
damaged because of stack wrapping.
Because the value of the STK_PP register can change at
any time, it is theoretically possible to manage the stack in
such a way as to allow it to grow beyond one SRAM page or
manage multiple stacks. However, the only supported use of
the STK_PP register is when its value is set before the first
stack operation and not changed again.
4.1.3
Interrupts
Interrupts, in a multipage SRAM enCoRe V device, operate
the same as interrupts in a 256-byte device. However,
because the CPU_F register is automatically set to 00h on
an interrupt and because of the nonlinear nature of inter-
rupts in a system, other parts of the memory paging archi-
tecture can be affected.
Interrupts are an abrupt change in program flow. If no spe-
cial action is taken on interrupts by the enCoRe V device,
the
interrupt service routine (ISR)
could be thrown into
any SRAM page. To prevent this problem, the special
addressing modes for all memory accesses, except for
stack and
MVI
, are disabled when an ISR is entered. The
special addressing modes are disabled when the CUP_F
register is cleared. At the end of the ISR, the previous
SRAM addressing mode is restored when the CPU_F regis-
ter value is restored by the
RETI
instruction.
All interrupt service
code starts execution in SRAM
Page 0. If the ISR must change to another SRAM page, do
this by changing the values of the CPU_F[7:6] bits to enable
the special SRAM addressing modes. However, any change
made to the CUR_PP, IDX_PP, or STK_PP registers per-
sists after the ISR returns. Therefore, have the ISR save the
current value of any paging register it modifies and restore
its value before the ISR returns.
4.1.4
MVI Instructions
MVI
instructions use data page pointers of their own
(MVR_PP and MVW_PP). This allows a data buffer to be
located away from other program variables, but accessible
without changing the Current Page Pointer (CUR_PP).
An
MVI
instruction performs three memory operations. Both
forms of the
MVI
instruction access an address in SRAM
that holds the data pointer (a memory read 1st access),
incrementing that value and then storing it back in SRAM (a
memory write 2nd access). This pointer value must reside in
the current page, just as all other nonstack and nonindexed
operations on memory. However, the third memory opera-
tion uses the MVx_PP register. This third memory access is
either a read or a write, depending upon which
MVI
instruc-
tion is used. The MVR_PP pointer is used for the
MVI
instruction that moves data into the accumulator. The
MVW_PP pointer is used for the
MVI
instruction that moves
data from the accumulator into SRAM. The
MVI
pointers are
always enabled, regardless of the state of the Flag register
page bits (CPU_F register).
4.1.5
Current Page Pointer
The Current Page Pointer determines which SRAM page is
used for all memory accesses. Normal memory accesses
are those not covered by other pointers including all non-
stack, non-
MVI
, and nonindexed memory access instruc-
tions. The normal memory access instructions have the
SRAM page they operate on determined by the value of the
CUR_PP register. By default, the CUR_PP register has no
affect on the SRAM page that is used for normal memory
access, because all normal memory access is forced to
SRAM Page 0.
The upper bit of the PgMode bits in the CPU_F register
determine if the CUR_PP register affects normal memory
access. When the upper bit of the PgMode bits is set to ‘0’,
all normal memory access is forced to SRAM Page 0. This
mode is automatically enabled when an Interrupt Service
Routine (ISR) is entered. This is because, before the ISR is
entered, the M8C pushes the current value of the CPU_F
register onto the stack and then clears the CPU_F register.
Therefore, by default, any normal memory access in an ISR
is guaranteed to occur in SRAM Page 0.
When the
RETI
instruction is executed to end the ISR, the
previous value of the CPU_F register is restored, returning
to the previous page mode. This is the default ISR behavior
and it is possible to change the PgMode bits in the CPU_F
register while in an ISR. If the PgMode bits are changed
while in an ISR, the pre-ISR value is still restored by the
RETI
; but if the CUR_PP register is changed in the ISR, the
ISR is also required to restore the value before executing
the
RETI
instruction.
When the upper bit of the PgMode bits is set to ‘1‘, all nor-
mal memory access is forced to the SRAM page indicated
by the CUR_PP register value.
summarizes the
PgMode bit values and the corresponding Memory Paging
mode.
