enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H
237
1,EDh
21.4.25 SLP_CFG3
Sleep Configuration Register 3
This register holds the configuration of the wakeup sequence taps.
It is strongly recommended to not alter this register setting
.
In the table, note that the reserved bit is a grayed table cell and is not described in the bit description section. Reserved bits
must always be written with a value of ‘0’. For additional information, refer to the
Register Definitions on page 82
in the Sleep
and Watchdog chapter.
6
DBL_TAPS
When this bit is set all the tap values (T0, T1, and T2) are doubled for the wakeup sequence.
5:4
T2TAP[1:0]
These bits control the duration of the T2-T4 sequence (see
) by selecting a
tap from the WakeupTimer.
Note
The T2 delay is only valid for the wakeup sequence. It is not used
for the buzz sequence.
00
1 µs
01
2 µs
10
5 µs
11
10 µs
3:2
T1TAP[1:0]
These bits control the duration of the T1-T2 sequence (see
) by selecting a
tap from the Wakeup Timer.
00
3 µs
01
4 µs
10
5 µs
11
10 µs
1:0
T0TAP[1:0]
These bits control the duration of the T0-T1 sequence (see
) by selecting a
tap from the Wakeup Timer.
00
10 µs
01
14 µs
10
20 µs
11
30 µs
Individual Register Names and Addresses:
1,EDh
SLP_CFG3 : 1,EDh
7
6
5
4
3
2
1
0
Access : POR
RW : 1
RW : 11
RW : 11
RW : 11
Bit Name
DBL_TAPS
T2TAP[1:0]
T1TAP[1:0]
T0TAP[1:0]
Bit
Name
Description
