enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H
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0,36h
21.3.11 EP0_CR
Endpoint 0 Control Register
This register is an endpoint 0 control register.
For additional information, refer to the
Register Definitions on page 147
in the Full-Speed USB chapter.
7
Setup Received
When set, this bit indicates a valid setup packet was received and ACKed.
6
IN Received
When set, this bit indicates a valid IN packet was received.
5
OUT Received
When set, this bit indicates an OUT packet was received.
4
ACKed Transaction
When set, this bit indicates a valid OUT packet has been received and ACKed.
3:0
Mode[3:0]
The mode bits control how the USB SIE responds to traffic and how the USB SIE changes the mode
of that endpoint as a result of host packets to the endpoint.
Individual Register Names and Addresses:
0,36h
EP0_CR : 0,36h
7
6
5
4
3
2
1
0
Access : POR
RC : 0
RC : 0
RC : 0
RC : 0
RW : 0
Bit Name
Setup
Received
IN Received
OUT Received
ACKed
Transaction
Mode[3:0]
Bit
Name
Description
