enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H
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Section D: Registers
The Registers section discusses the registers of the enCoRe V device. It lists all the registers in mapping tables, in address
order. For easy reference, each register is linked to the page of a detailed description located in the next chapter. This section
includes the following chapter:
■
Register Reference chapter on page 163
Register General Conventions
The register conventions specific to this section and the
Register Reference chapter are listed in the following table:
Register Mapping Tables
The enCoRe V device has a total register address space of
512 bytes. The register space is also referred to as I/O
space and is broken into two parts: Bank 0 (user space) and
Bank 1 (configuration space). The XIO bit in the Flag regis-
ter (CPU_F) determines which bank the user is currently in.
When the XIO bit is set, the user is said to be in the
“extended” address space or the “configuration” registers.
Refer to the individual enCoRe V device datasheets for
device-specific register mapping information.
Register Conventions
Convention
Description
Empty, grayed-out
table cell
Illustrates a reserved bit or group of bits.
‘x’ before the comma
in an address
Indicates the register exists in register bank 1 and
register bank 2.
‘x’ in a register name
Indicates that there are multiple instances/address
ranges of the same register.
R
Read register or bit(s).
W
Write register or bit(s).
O
Only a read/write register or bit(s).
L
Logical register or bit(s).
C
Clearable register or bit(s).
#
Access is bit specific.
