enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H
153
Full-Speed USB
20.3.10 EPx_CR0 Register
The Endpoint Control Register 0 (EPx_CR0) is used for sta-
tus and configuration of the non-control endpoints 1 to 8.
Bit 7: Stall.
When this bit is set, the SIE stalls an OUT
packet if the mode bits are set to ACK-OUT. The SIE stalls
an IN packet if the mode bits are set to ACK-IN. This bit
must be cleared for all other modes. ‘0’ is do not issue a
stall. ‘1’ is stall an OUT packet if mode bits are set to ACK-
OUT, or stall an IN packet if mode bits are set to ACK-IN.
Bit 5: NAK Int Enable.
When set, this bit causes an end-
point interrupt to be generated even when a transfer com-
pletes with a NAK. ‘0’ is do not issue an interrupt after
completing the transaction by sending NAK. ‘1’ is interrupt
after transaction is complete by sending NAK.
Bit 4: ACKed Transaction.
The ACKed Transaction bit is
set whenever the SIE engages in a transaction to the regis-
ter's endpoint that completes with an ACK packet. This bit is
cleared by any writes to the register. ‘0’ is no ACKed trans-
actions since bit was last cleared. ‘1’ indicates a transaction
ended with an ACK.
Bits 3 to 0: Mode[3:0].
The mode controls how the USB
SIE responds to traffic and how the USB SIE changes the
mode of that endpoint as a result of host packets to the end-
point. Refer to
“Mode Encoding for Control and Non-Control
.
For additional information, refer to the
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Access
1,54h
EP1_CR0
Stall
NAK_INT_EN
ACKed Tx
Mode[3:0]
# : 00
1,55h
EP2_CR0
Stall
NAK_INT_EN
ACKed Tx
Mode[3:0]
# : 00
1,56h
EP3_CR0
Stall
NAK_INT_EN
ACKed Tx
Mode[3:0]
# : 00
1,57h
EP4_CR0
Stall
NAK_INT_EN
ACKed Tx
Mode[3:0]
# : 00
1,58h
EP5_CR0
Stall
NAK_INT_EN
ACKed Tx
Mode[3:0]
# : 00
1,59h
EP6_CR0
Stall
NAK_INT_EN
ACKed Tx
Mode[3:0]
# : 00
1,5Ah
EP7_CR0
Stall
NAK_INT_EN
ACKed Tx
Mode[3:0]
# : 00
1,5Bh
EP8_CR0
Stall
NAK_INT_EN
ACKed Tx
Mode[3:0]
# : 00
