Cypress enCoRe V CY7C643 Series, Technical Reference Manual

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enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 127
SPI
Control Register
18.2.3 SPI_CR Register
The SPI Control Register (SPI_CR) is the SPI’s control reg-
ister.
Bit 7: LSb First. This bit determines how the serial data is
shifted out, either LSb or MSb first.
Bit 6: Overrun. This status bit indicates whether there was
a receive buffer overrun. A read from the receive buffer after
each received byte must be performed before the reception
of the next byte to avoid an overrun condition.
Bit 5: SPI Complete.
This status bit indicates the comple-
tion of a transaction. A read from this register clears this bit.
Bit 4: TX Reg Empty. This status bit indicates whether the
Transmit register is empty.
Bit 3: RX Reg Full. This status bit indicates a Receive reg-
ister full condition.
Bit 2: Clock Phase. This bit determines the edge (rising or
falling) on which the data changes.
Bit 1: Clock Polarity. This bit determines the logic level the
clock codes to in its idle state.
Bit 0: Enable. This bit enables the SPI block.
For additional information, refer to the SPI_CR register on
page 168 .
18.2.3.1 SPI Control Register Definitions
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
0,2Bh SPI_CR LSb First Overrun
SPI
Complete
TX Reg
Empty
RX Reg Full
Clock
Phase
Clock
Polarity
Enable # : 00
Legend
# Access is bit specific. Refer to the register detail for additional information.
Table 18-4. SPI Control Register Descriptions
Bit # Name Access Description
7 LSb First Read/Write
0 = Data shifted out MSb First.
1 = Data shifted out LSb First.
6 Overrun Read Only
0 = No overrun.
1 = Indicates new byte received before previous one is read.
5 SPI Complete Read Only
0 = Transaction in progress.
1 = Transaction is complete. Reading SPI_CR clears this bit.
4 TX Reg Empty Read Only
0 = TX register is full.
1 = TX register is empty. Writing SPI_TXR register clears this bit.
3 RX Reg Full Read Only
0 = RX register is not full.
1 = RX register is full. Reading SPI_RXR register clears this bit.
2 Clock Phase Read/Write
0 = Data changes on trailing edge.
1 = Data changes on leading clock edge.
1 Clock Polarity Read/Write
0 = Non-inverted, clock idles low (modes 0, 2).
1 = Inverted, clock idles high (modes 1, 3).
0 Enable Read/Write
0 = Disable SPI function.
1 = Enable SPI function.