Cypress enCoRe V CY7C643 Series, Technical Reference Manual

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enCoRe™ V CY7C643xx, enCoRe™ V LV CY7C604xx TRM, Document No. 001-32519 Rev *H 126
SPI
18.2.2 SPI_RXR Register
The SPI Receive Data Register (SPI_RXR) is the SPI’s
receive data register. A write to this register clears the RX
Reg Full status bit in the Control register (SPI_CR).
Bits 7 to 0: Data[7:0].
These bits encompass the SPI
Receive register. They are discussed by function type in
Table 18-2 and Table 18-3 .
For additional information, refer to the SPI_RXR register on
page 167 .
18.2.2.1 SPI Master Data Register Definitions
There are two 8-bit Data registers and one 8-bit Control/Status register. Table 18-2 explains the meaning of the Transmit and
Receive registers in the context of SPIM operation.
18.2.2.2 SPI Slave Data Register Definitions
There are two 8-bit Data registers and one 8-bit Control/Status register. Table 18-3 explains the meaning of the Transmit and
Receive registers in the context of SPIS operation.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access
0,2Ah SPI_RXR Data[7:0] R : 00
Table 18-2. SPIM Data Register Descriptions
Name Function Description
SPI_TXR TX Buffer
Write only register.
If no transmission is in progress and this register is written to, the data from this register is loaded into the Shift register on
the following clock edge, and a transmission is initiated. If a transmission is currently in progress, this register serves as a
buffer for TX data.
This register must only be written to when TX Reg Empty status is set and the write clears the TX Reg Empty status bit in the
Control register. When the data is transferred from this register to the Shift register, then TX Reg Empty status is set.
SPI_RXR RX Buffer
Read-only register.
When a byte transmission/reception is complete, the data in the shifter is transferred into the RX Buffer register and RX Reg
Full status is set in the Control register.
A read from this register clears the RX Reg Full status bit in the Control register.
Table 18-3. SPIS Data Register Descriptions
Name Function Description
SPI_TXR TX Buffer
Write only register.
This register must only be written to when TX Reg Empty status is set and the write clears the TX Reg Empty status bit in the
Control register. When the data is transferred from this register to the Shift register, then TX Reg Empty status is set.
SPI_RXR RX Buffer
Read-only register.
When a byte transmission/reception is complete, the data in the shifter is transferred into the RX Buffer register and RX Reg
Full status is set in the Control register.
A read from this register clears the RX Reg Full status bit in the Control register.