Cypress CY8C28 series, Technical Reference Manual

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CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G 51
Supervisory ROM (SROM)
Address F8h is the return code byte for all SROM functions
(except Checksum and TableRead); for this function, the
only acceptable values are 00h and 02h. Address FCh is the
fail count variable. After POR (Power on Reset), WDR, or
XRES (External Reset), the variable is initialized to 00h by
the SROM. Each time the checksum fails, the fail count is
incremented. Therefore, if it takes two passes through
SWBootReset to get a good checksum, the fail count is 01h.
3.1.2.2 HWBootReset Function
The HWBootReset function forces a hardware reset of the
PSoC. A hardware rest causes all registers to return to their
POR state. Then, the SROM SWBootReset function exe-
cutes, followed by Flash code execution beginning at
address 0x0000.
The HWBootReset function only requires that the CPU_A,
KEY1, and KEY2 be setup correctly. As with all other SROM
functions, if the setup is incorrect, the SROM executes a
HALT. Then, either a POR, XRES, or WDR is needed to
clear the HALT. See the
System Resets chapter on
page 123 for more information.
3.1.2.3 ReadBlock Function
The ReadBlock function reads 64 contiguous bytes from
Flash: a
block . The CY8C28xxx PSoC devices have 16 KB
of Flash and therefore have 256 64-byte blocks. Valid block
IDs are 0x00 to 0xFF.
The first thing the ReadBlock function does is to check the
protection bits to determine if the desired BLOCKID is read-
able. If read protection is turned on, the ReadBlock function
exits setting the accumulator and KEY2 back to 00h. KEY1
has a value of 01h indicating a read failure.
If read protection is not enabled, the function reads 64 bytes
from the Flash using a ROMX instruction and stores the
results in SRAM using an MVI instruction. The 64 bytes are
stored in SRAM, beginning at the address indicated by the
value of the POINTER parameter. When the ReadBlock
completes successfully, the accumulator, KEY1, and KEY2
will all have a value of 00h.
Note A MVI [expr], A is used to store the Flash block con-
tents in SRAM; thus, you can the MVW_PP register to indi-
cate which SRAM pages receive the data.
Table 3-4. SRAM Map Post SWBootReset (00h)
Address
0 1 2 3 4 5 6 7
8 9 A B C D E F
0x0_
0x00 0x00 0x00 ?? ?? ?? ?? ??
?? ?? ?? ?? ?? ?? ?? ??
0x1_
?? ?? ?? ?? ?? ?? ?? ??
?? ?? ?? ?? ?? ?? ?? ??
0x2_
?? ?? ?? ?? ?? ?? ?? ??
?? ?? ?? ?? ?? ?? ?? ??
0x3_
?? ?? ?? ?? ?? ?? ?? ??
?? ?? ?? ?? ?? ?? ?? ??
0x4_
?? ?? ?? ?? ?? ?? ?? ??
?? ?? ?? ?? ?? ?? ?? ??
0x5_
?? ?? ?? ?? ?? ?? ?? ??
?? ?? ?? ?? ?? ?? ?? ??
0x6_
?? ?? ?? ?? ?? ?? ?? ??
?? ?? ?? ?? ?? ?? ?? ??
0x7_
?? ?? ?? ?? ?? ?? ?? ??
?? ?? ?? ?? ?? ?? ?? ??
0x8_
?? ?? ?? ?? ?? ?? ?? ??
?? ?? ?? ?? ?? ?? ?? ??
0x9_
?? ?? ?? ?? ?? ?? ?? ??
?? ?? ?? ?? ?? ?? ?? ??
0xA_
?? ?? ?? ?? ?? ?? ?? ??
?? ?? ?? ?? ?? ?? ?? ??
0xB_
?? ?? ?? ?? ?? ?? ?? ??
?? ?? ?? ?? ?? ?? ?? ??
0xC_
?? ?? ?? ?? ?? ?? ?? ??
?? ?? ?? ?? ?? ?? ?? ??
0xD_
?? ?? ?? ?? ?? ?? ?? ??
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0xE_
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0xF_
0x00 0x00 0x00 0x00 0x00 0x00 ?? ??
0x00
0x02
xx 0x00 0x00 0xn xx 0x00 0x00
Table 3-5. HWBootReset Parameters (0Fh)
Name Address Type Description
KEY1 0,F8h RAM 3Ah
KEY2 0,F9h RAM
Stack Pointer value+3, when SSC is
executed.
Table 3-6. Flash Memory Organization
PSoC Device
Amount of
Flash
Amount of
SRAM
Number of
Blocks
per Bank
Number of
Banks
CY8C28xxx 16 KB 1 KB 128 2
Table 3-7. ReadBlock Parameters (01h)
Name Address Type Description
MVW_PP 0,D5h Register MVI write page pointer register
KEY1 0,F8h RAM 3Ah
KEY2 0,F9h RAM
Stack Pointer value+3, when SSC is
executed.
BLOCKID 0,FAh RAM Flash block number
POINTER 0,FBh RAM
Addresses in SRAM where returned
data should be stored.