Document Number: 002-00856 Rev. *E
S29JL064J
Figure 8.3
Secured Silicon Region Protect Verify
8.14
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent
writes (refer to
for command definitions). In addition, the following hardware data protection measures prevent
accidental erasure or programming, which might otherwise be caused by spurious system level signals during V
CC
power-up and
power-down transitions, or from system noise.
8.14.1
Low V
CC
Write Inhibit
When V
CC
is less than V
LKO
, the device does not accept any write cycles. This protects data during V
CC
power-up and power-down.
The command register and all internal program/erase circuits are disabled, and the device resets to the read mode. Subsequent
writes are ignored until V
CC
is greater than V
LKO
. The system must provide the proper signals to the control pins to prevent
unintentional writes when V
CC
is greater than V
LKO
.
8.14.2
Write Pulse Glitch Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
8.14.3
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = V
IL
, CE# = V
IH
or WE# = V
IH
. To initiate a write cycle, CE# and WE# must be
a logical zero while OE# is a logical one.
8.14.4
Power-Up Write Inhibit
If WE# = CE# = V
IL
and OE# = V
IH
during power up, the device does not accept commands on the rising edge of WE#. The internal
state machine is automatically reset to the read mode on power-up.
Write 60h to
any address
Write 40h to Secure
Silicon Region address
with A6 = 0,
A1 = 1, A0 = 0
START
RESET# =
V
IH
or V
ID
Wait 1 ms
Read from Secure
Silicon Region address
with A6 = 0,
A1 = 1, A0 = 0
If data = 00h,
Secure Silicon Region
is unprotected.
If data = 01h,
Secure Silicon Region
is protected.
Remove V
IH
or V
ID
from RESET#
Secure Silicon Region
Protect Verify
complete
Secured Silicon Region
exit command
