Cypress Semiconductor NoBL CY7C1355C Specification Sheet Download Page 3 | Manualshive

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CY7C1355C
CY7C1357C

Document #: 38-05539 Rev. *E

Page 3 of 28

Pin Configurations

100-Pin TQFP Pinout

A

A

A

A

A1

A0

NC

/288M

NC/144M

V

SS

V

DD

NC/36M

A

A

A

A

A

A

DQP

B

DQ

B

DQ

B

V

DDQ

V

SS

DQ

B

DQ

B

DQ

B

DQ

B

V

SS

V

DDQ

DQ

B

DQ

B

V

SS

NC

V

DD

DQ

A

DQ

A

V

DDQ

V

SS

DQ

A

DQ

A

DQ

A

DQ

A

V

SS

V

DDQ

DQ

A

DQ

A

DQP

A

DQP

C

DQ

C

DQ

C

V

DDQ

V

SS

DQ

C

DQ

C

DQ

C

DQ

C

V

SS

V

DDQ

DQ

C

DQ

C

Vss/DNU

V

DD

NC

V

SS

DQ

D

DQ

D

V

DDQ

V

SS

DQ

D

DQ

D

DQ

D

DQ

D

V

SS

V

DDQ

DQ

D

DQ

D

DQP

D

A

A

CE

1

CE

2

BW

D

BW

C

BW

B

BW

A

CE

3

V

DD

V

SS

CLK

WE

CEN

OE

NC

/18M

A

A

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

A

A

ADV/LD

ZZ

MODE

NC

/7

2

M

CY7C1355C

BYTE A

BYTE B

BYTE D

BYTE C

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Summary of Contents for NoBL CY7C1355C

Page 1: ... Burst SRAM designed specifically to support unlimited true back to back Read Write operations without the insertion of wait states The CY7C1355C CY7C1357C is equipped with the advanced No Bus Latency NoBL logic required to enable consecutive Read Write operations with data being transferred on every clock cycle This feature dramatically improves the throughput of data through the SRAM especially ...

Page 2: ...G S E N S E A M P S WRITE ADDRESS REGISTER A0 A1 A O U T P U T B U F F E R S E ZZ SLEEP CONTROL Logic Block Diagram CY7C1355C 256K x 36 C MODE BWA BWB WE CE1 CE2 CE3 OE READ LOGIC DQs DQPA DQPB MEMORY ARRAY E INPUT REGISTER ADDRESS REGISTER WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC BURST LOGIC A0 A1 D1 D0 Q1 Q0 A0 A1 ADV LD CE ADV LD C CLK CEN WRITE DRIVERS D A T A S T E E R I N G S E N S E ...

Page 3: ...Q DQC DQC Vss DNU VDD NC VSS DQD DQD VDDQ VSS DQD DQD DQD DQD VSS VDDQ DQD DQD DQPD A A CE 1 CE 2 BW D BW C BW B BW A CE 3 V DD V SS CLK WE CEN OE NC 18M A A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 9...

Page 4: ... VSS VDDQ DQB DQB Vss DNU VDD NC VSS DQB DQB VDDQ VSS DQB DQB DQPB NC VSS VDDQ NC NC NC A A CE 1 CE 2 NC NC BW B BW A CE 3 V DD V SS CLK WE CEN OE NC 18M A A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 9...

Page 5: ...V LD NC CE1 OE A WE VSS VSS VSS VSS VSS VSS VSS VSS DQPA MODE DQPD DQPB BWB BWC NC VDD NC BWA NC CEN BWD ZZ 2 3 4 5 6 7 1 A B C D E F G H J K L M N P R T U VDDQ NC 576M NC 1G NC DQB DQB DQB DQB A A A A NC 18M VDDQ CE2 A NC VDDQ NC VDDQ VDDQ VDDQ NC NC NC 144M NC 72M VDDQ VDD CLK VDD VSS VSS VSS VSS VSS VSS VSS VSS NC NC NC NC TDO TCK TDI TMS A A NC 288M VDDQ VDDQ VDDQ A NC 36M A A CE3 A A A A A A ...

Page 6: ...QB NC DQB NC DQA DQA VDD VDDQ VDD VDDQ DQB VDD NC VDD DQA VDD VDDQ DQA VDDQ VDD VDD VDDQ VDD VDDQ DQA VDDQ A A VSS A A A DQB DQB DQB ZZ DQA DQA DQPA DQA A VDDQ A A0 A VSS NC CY7C1357C 512K x 18 2 3 4 5 6 7 1 A B C D E F G H J K L M N P R TDO NC 576M NC 1G NC NC DQPB NC DQB CE1 NC CE3 BWB CEN A CE2 NC DQB DQB MODE NC DQB DQB NC NC NC NC 36M NC 72M VDDQ NC BWA CLK WE VSS VSS VSS VSS VDDQ VSS VDD VSS...

Page 7: ...Synchronous Clock Enable Input active LOW When asserted LOW the Clock signal is recognized by the SRAM When deasserted HIGH the Clock signal is masked Since deasserting CEN does not deselect the device CEN can be used to extend the previous cycle when required ZZ Input Asynchronous ZZ Sleep Input This active HIGH input places the device in a non time critical sleep condition with data integrity pr...

Page 8: ...sequence of the burst counter is determined by the MODE input signal A LOW input on MODE selects a linear burst mode a HIGH selects an interleaved burst sequence Both burst counters use A0 and A1 in the burst sequence and will wrap around when incremented suffi ciently A HIGH input on ADV LD will increment the internal burst counter regardless of the state of chip enable inputs or WE WE is latched...

Page 9: ...stics Parameter Description Test Conditions Min Max Unit IDDZZ Sleep mode standby current ZZ VDD 0 2V 50 mA tZZS Device operation to ZZ ZZ VDD 0 2V 2tCYC ns tZZREC ZZ recovery time ZZ 0 2V 2tCYC ns tZZI ZZ active to sleep current This parameter is sampled 2tCYC ns tRZZI ZZ Inactive to exit sleep current This parameter is sampled 0 ns Truth Table 2 3 4 5 6 7 8 Operation Address Used CE1 CE2 CE3 ZZ ...

Page 10: ...te A DQA and DQPA L L H H H Write Byte B DQB and DQPB L H L H H Write Byte C DQC and DQPC L H H L H Write Byte D DQD and DQPD L H H H L Write All Bytes L L L L L Truth Table for Read Write 2 3 9 Function CY7C1357C WE BWA BWB Read H X X Write No bytes written L H H Write Byte A DQA and DQPA L H H Write Byte B DQB and DQPB L H H Write All Bytes L L L Note 9 Table only lists a partial listing of the ...

Page 11: ...gic HIGH level Test Data In TDI The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register TDI is internally pulled up and can be unconnected if the TAP is unused in an application TDI is connected to the most signif ica...

Page 12: ...ller enters the Shift DR state The IDCODE instruction is loaded into the instruction register upon power up or whenever the TAP controller is given a test logic reset state SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift DR state The SAMPLE Z command puts the output bus into a High Z state until ...

Page 13: ...MSS TMS Set Up to TCK Clock Rise 5 ns tTDIS TDI Set Up to TCK Clock Rise 5 ns tCS Capture Set Up to TCK Rise 5 ns Hold Times tTMSH TMS Hold after TCK Clock Rise 5 ns tTDIH TDI Hold after Clock Rise 5 ns tCH Capture Hold after Clock Rise 5 ns Notes 10 tCS and tCH refer to the set up and hold time requirements of latching data from the boundary scan register 11 Test conditions are specified using th...

Page 14: ...mA VDDQ 2 5V 2 4 V 2 0 V VOH2 Output HIGH Voltage IOH 100 µA VDDQ 3 3V 2 9 V VDDQ 2 5V 2 1 V VOL1 Output LOW Voltage IOL 8 0 mA VDDQ 3 3V 0 4 V IOL 8 0 mA VDDQ 2 5V 0 4 V VOL2 Output LOW Voltage IOL 100 µA VDDQ 3 3V 0 2 V VDDQ 2 5V 0 2 V VIH Input HIGH Voltage VDDQ 3 3V 2 0 VDD 0 3 V VDDQ 2 5V 1 7 VDD 0 3 V VIL Input LOW Voltage VDDQ 3 3V 0 5 0 7 V VDDQ 2 5V 0 3 0 7 V IX Input Load Current GND VIN...

Page 15: ...etween TDI and TDO This operation does not affect SRAM operations SAMPLE Z 010 Captures I O ring contents Places the boundary scan register between TDI and TDO Forces all SRAM output drivers to a High Z state RESERVED 011 Do Not Use This instruction is reserved for future use SAMPLE PRELOAD 100 Captures I O ring contents Places the boundary scan register between TDI and TDO Does not affect SRAM op...

Page 16: ...B 14 E7 DQB 50 K2 DQD 14 E7 DQA 50 K2 DQB 15 F6 DQB 51 Internal Internal 15 F6 DQA 51 Internal Internal 16 G7 DQB 52 H1 DQC 16 G7 DQA 52 H1 DQB 17 H6 DQB 53 G2 DQC 17 H6 DQA 53 G2 DQB 18 T7 ZZ 54 E2 DQC 18 T7 ZZ 54 E2 DQB 19 K7 DQA 55 D1 DQC 19 K7 DQA 55 D1 DQB 20 L6 DQA 56 H2 DQC 20 L6 DQA 56 Internal Internal 21 N6 DQA 57 G1 DQC 21 N6 DQA 57 Internal Internal 22 P7 DQA 58 F2 DQC 22 P7 DQA 58 Int...

Page 17: ...DQB 50 J1 DQD 14 D11 DQA 50 J1 DQB 15 E11 DQB 51 Internal Internal 15 E11 DQA 51 Internal Internal 16 F11 DQB 52 G2 DQC 16 F11 DQA 52 G2 DQB 17 G11 DQB 53 F2 DQC 17 G11 DQA 53 F2 DQB 18 H11 ZZ 54 E2 DQC 18 H11 ZZ 54 E2 DQB 19 J10 DQA 55 D2 DQC 19 J10 DQA 55 D2 DQB 20 K10 DQA 56 G1 DQC 20 K10 DQA 56 Internal Internal 21 L10 DQA 57 F1 DQC 21 L10 DQA 57 Internal Internal 22 M10 DQA 58 E1 DQC 22 M10 D...

Page 18: ...t HIGH Voltage 13 for 3 3V I O 2 0 VDD 0 3V V for 2 5V I O 1 7 VDD 0 3V V VIL Input LOW Voltage 13 for 3 3V I O 0 3 0 8 V for 2 5V I O 0 3 0 7 V IX Input Leakage Current except ZZ and MODE GND VI VDDQ 5 5 µA Input Current of MODE Input VSS 30 µA Input VDD 5 µA Input Current of ZZ Input VSS 5 µA Input VDD 30 µA IOZ Output Leakage Current GND VI VDDQ Output Disabled 5 5 µA IDD VDD Operating Supply C...

Page 19: ...to Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance per EIA JESD51 29 41 34 1 16 8 C W ΘJC Thermal Resistance Junction to Case 6 31 14 0 3 0 C W AC Test Loads and Waveforms Note 15 Tested initially and after any design or process change that may affect these parameters OUTPUT R 317Ω R 351Ω 5 pF INCLUDING JIG AND SCOPE a b OUTPUT RL 50Ω Z0 50Ω VT 1...

Page 20: ...Rise 0 5 0 5 ns tALH ADV LD Hold after CLK Rise 0 5 0 5 ns tWEH WE BWX Hold after CLK Rise 0 5 0 5 ns tCENH CEN Hold after CLK Rise 0 5 0 5 ns tDH Data Input Hold after CLK Rise 0 5 0 5 ns tCEH Chip Enable Hold after CLK Rise 0 5 0 5 ns Notes 16 Timing reference level is 1 5V when VDDQ 3 3V and is 1 25V when VDDQ 2 5V 17 Test conditions shown in a of AC Test Loads unless otherwise noted 18 This pa...

Page 21: ...t sequence is determined by the status of the MODE 0 Linear 1 Interleaved Burst operations are optional WRITE D A1 1 2 3 4 5 6 7 8 9 CLK tCYC tCL tCH 10 CE tCEH tCES WE CEN tCENH tCENS BWX ADV LD tAH tAS ADDRESS A1 A2 A3 A4 A5 A6 A7 tDH tDS DQ COMMAND tCLZ D A1 D A2 Q A4 Q A3 D A2 1 tDOH tCHZ tCDV WRITE D A2 BURST WRITE D A2 1 READ Q A3 READ Q A4 BURST READ Q A4 1 WRITE D A5 READ Q A6 WRITE D A7 D...

Page 22: ...ing this cycle Switching Waveforms continued WRITE D A1 1 2 3 4 5 6 7 8 9 CLK tCYC tCL tCH 10 CE tCEH tCES WE CEN tCENH tCENS BWX ADV LD tAH tAS ADDRESS A1 A2 A3 A4 A5 A6 A7 tDH tDS DQ COMMAND tCLZ D A1 D A2 Q A4 Q A3 D A2 1 tDOH tCHZ tCDV WRITE D A2 BURST WRITE D A2 1 READ Q A3 READ Q A4 BURST READ Q A4 1 WRITE D A5 READ Q A6 WRITE D A7 DESELECT OE tOEV tOELZ tOEHZ DON T CARE UNDEFINED D A5 tDOH ...

Page 23: ...lected when entering ZZ mode See truth table for all possible signal conditions to deselect the device 27 DQs are in high Z when exiting ZZ sleep mode Switching Waveforms continued t ZZ I SUPPLY CLK ZZ t ZZREC ALL INPUTS except ZZ DON T CARE I DDZZ t ZZI tRZZI Outputs Q High Z DESELECT or READ Only Feedback ...

Page 24: ...id Array 14 x 22 x 2 4 mm Lead Free CY7C1357C 133BGXI CY7C1355C 133BZI 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1357C 133BZI CY7C1355C 133BZXI 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Lead Free CY7C1357C 133BZXI 100 CY7C1355C 100AXC 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Commercial CY7C1357C 100AXC CY7C1355C 100BGC 51 85115 119...

Page 25: ...IN MILLIMETERS BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 0 30 0 08 0 65 20 00 0 10 22 00 0 20 1 40 0 05 12 1 1 60 MAX 0 05 MIN 0 60 0 15 0 MIN 0 25 0 7 8X STAND OFF R 0 08 MIN TYP 0 20 MAX 0 15 MAX 0 20 MAX R 0 08 MIN 0 20 MAX 14 00 0 10 16 00 0 20 0 10 SEE DETAIL A DETAIL A 1 100 30 31 50 51 80 81 GAUGE PLANE 1 00 REF 0 20 MIN SEATING PLANE 100 Pin Thin Plastic Quad...

Page 26: ... J U P N M T R 12 00 19 50 30 TYP 2 40 MAX A1 CORNER 0 70 REF U T R P N M L K J H G F E D C A B 2 1 4 3 6 5 7 Ø1 00 3X REF 7 62 22 00 0 20 14 00 0 20 1 27 0 60 0 10 C 0 15 C B A 0 15 4X Ø0 05 M C Ø0 75 0 15 119X Ø0 25 M C A B SEATING PLANE 0 90 0 05 3 81 10 16 0 25 C 0 56 51 85115 B 119 Ball BGA 14 x 22 x 2 4 mm 51 85115 Feedback ...

Page 27: ...ctor Corporation ZBT is a trademark of Integrated Device Technology Inc All product and company names mentioned in this document are the trademarks of their respective holders A 1 PIN 1 CORNER 15 00 0 10 13 00 0 10 7 00 1 00 Ø0 50 165X Ø0 25 M C A B Ø0 05 M C B A 0 15 4X 0 35 0 06 SEATING PLANE 0 53 0 05 0 25 C 0 15 C PIN 1 CORNER TOP VIEW BOTTOM VIEW 2 3 4 5 6 7 8 9 10 10 00 14 00 B C D E F G H J...

Page 28: ...Changed ΘJA and ΘJc for BGA Package from 25 and 6 C W to 34 1 and 14 0 C W respectively Changed ΘJA and ΘJc for FBGA Package from 27 and 6 C W to 16 8 and 3 0 C W respectively Added lead free information for 100 pin TQFP 119 BGA and 165 FBGA Packages Updated Ordering Information Table Changed from Preliminary to Final B 351895 See ECN PCI Changed ISB2 from 30 to 40 mA Updated Ordering Information ...

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